Patent
US 10,147,789PROCESS FOR FABRICATING VERTICALLY-ALIGNED GALLIUM ARSENIDE SEMICONDUCTOR NANOWIRE ARRAY OF LARGE AREA
Woo LEE
US
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US 10,147,789Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flow chart illustrating a method for fabricating a gallium arsenide semiconductor nanowire array according to an exemplary embodiment of the present …
FIG. 2. Then, as illustrated in
FIG. 3 is a cross-sectional view illustrating a method for transferring the polystyrene nanoparticle monolayer array onto a surface of a gallium arsenide …
FIG. 4, diameters of polystyrene nanoparticles should be decreased through oxygen plasma treatment of the polystyrene nanoparticle monolayer array transferred …
FIG. 5 is a cross-sectional view illustrating a metal thin film deposited on the polystyrene nanoparticle monolayer array formed on the gallium arsenide …
FIG. 6 is a cross-sectional view illustrating a process for removing polystyrene according to an exemplary embodiment of the present invention. [0067]
FIG. 7 is a scanning electron microscope (SEM) photograph of the porous metal mesh 40 fabricated according to an exemplary embodiment of the present invention. …
FIG. 8 is a schematic view illustrating a method for fabricating the gallium arsenide semiconductor nanowires 60 using the porous metal mesh 40 according to an …
FIG. 9 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (100) gallium arsenide …
FIG. 10 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (111) gallium arsenide …
FIG. 11 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching a p-type (100) gallium arsenide …
FIG. 12 is an SEM photograph of a gallium arsenide semiconductor nanowire 60 array in a zigzag form fabricated by the porous metal mesh 40 at the time of …
FIG. 13 is an SEM photograph of the vertically-aligned gallium arsenide semiconductor nanowire 60 array having the porous surface, fabricated by the method …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a group I II -V compound semiconductor nanowire array, comprising: (a) preparing a patterned palladium containing metal mesh on a surface of a group I II -V compound semiconductor substrate; and (b) wet-etching the I II -V compound semiconductor substrate contacting the metal mesh in an etchant by applying an external bias for electrochemical etching to the metal mesh, wherein a voltage or a current is applied to the metal mesh forming an anode and the substrate contacting the anode is etched which lowers the metal mesh, and wherein a portion of the substrate that does not contact the anode is not etched forming a mesh shape. Currently amended
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein the metal mesh is formed of an alloy of two or more elements or is formed of two or more metals deposited as multiple layers. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein a length of a nanowire is controlled by a time in which the wet-etching is performed or is controlled by a magnitude of the applied bias. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein the etchant includes hydrofluoric acid (HF), hydrochloric acid (HCl), or nitric acid (HNO₃). Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, a nanowire is fabricated to be vertical to the substrate or is fabricated in a zigzag form. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, the bias is applied to the substrate to induce a nanowire to have a porous surface. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, a diameter of a nanowire is adjusted depending on a change in a size of a hole of the metal mesh. Previously presented
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein a group I II -V compound semiconductor is a gallium arsenide. Previously presented
2-3. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
vertically-aligned III-V compound semiconductor nanowire array
Materials described outside the worked examples.
gallium arsenide
GaAs
palladium-containing metal mesh
group III-V compound semiconductor
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a scanning electron microscope (SEM) photograph of the porous metal mesh 40 fabricated according to an exemplary embodiment of the present invention. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0.2–10 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,147,789Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flow chart illustrating a method for fabricating a gallium arsenide semiconductor nanowire array according to an exemplary embodiment of the present …
FIG. 2. Then, as illustrated in
FIG. 3 is a cross-sectional view illustrating a method for transferring the polystyrene nanoparticle monolayer array onto a surface of a gallium arsenide …
FIG. 4, diameters of polystyrene nanoparticles should be decreased through oxygen plasma treatment of the polystyrene nanoparticle monolayer array transferred …
FIG. 5 is a cross-sectional view illustrating a metal thin film deposited on the polystyrene nanoparticle monolayer array formed on the gallium arsenide …
FIG. 6 is a cross-sectional view illustrating a process for removing polystyrene according to an exemplary embodiment of the present invention. [0067]
FIG. 7 is a scanning electron microscope (SEM) photograph of the porous metal mesh 40 fabricated according to an exemplary embodiment of the present invention. …
FIG. 8 is a schematic view illustrating a method for fabricating the gallium arsenide semiconductor nanowires 60 using the porous metal mesh 40 according to an …
FIG. 9 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (100) gallium arsenide …
FIG. 10 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (111) gallium arsenide …
FIG. 11 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching a p-type (100) gallium arsenide …
FIG. 12 is an SEM photograph of a gallium arsenide semiconductor nanowire 60 array in a zigzag form fabricated by the porous metal mesh 40 at the time of …
FIG. 13 is an SEM photograph of the vertically-aligned gallium arsenide semiconductor nanowire 60 array having the porous surface, fabricated by the method …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a group I II -V compound semiconductor nanowire array, comprising: (a) preparing a patterned palladium containing metal mesh on a surface of a group I II -V compound semiconductor substrate; and (b) wet-etching the I II -V compound semiconductor substrate contacting the metal mesh in an etchant by applying an external bias for electrochemical etching to the metal mesh, wherein a voltage or a current is applied to the metal mesh forming an anode and the substrate contacting the anode is etched which lowers the metal mesh, and wherein a portion of the substrate that does not contact the anode is not etched forming a mesh shape. Currently amended
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein the metal mesh is formed of an alloy of two or more elements or is formed of two or more metals deposited as multiple layers. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein a length of a nanowire is controlled by a time in which the wet-etching is performed or is controlled by a magnitude of the applied bias. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein the etchant includes hydrofluoric acid (HF), hydrochloric acid (HCl), or nitric acid (HNO₃). Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, a nanowire is fabricated to be vertical to the substrate or is fabricated in a zigzag form. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, the bias is applied to the substrate to induce a nanowire to have a porous surface. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, a diameter of a nanowire is adjusted depending on a change in a size of a hole of the metal mesh. Previously presented
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein a group I II -V compound semiconductor is a gallium arsenide. Previously presented
2-3. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
vertically-aligned III-V compound semiconductor nanowire array
Materials described outside the worked examples.
gallium arsenide
GaAs
palladium-containing metal mesh
group III-V compound semiconductor
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a scanning electron microscope (SEM) photograph of the porous metal mesh 40 fabricated according to an exemplary embodiment of the present invention. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0.2–10 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,147,789Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flow chart illustrating a method for fabricating a gallium arsenide semiconductor nanowire array according to an exemplary embodiment of the present …
FIG. 2. Then, as illustrated in
FIG. 3 is a cross-sectional view illustrating a method for transferring the polystyrene nanoparticle monolayer array onto a surface of a gallium arsenide …
FIG. 4, diameters of polystyrene nanoparticles should be decreased through oxygen plasma treatment of the polystyrene nanoparticle monolayer array transferred …
FIG. 5 is a cross-sectional view illustrating a metal thin film deposited on the polystyrene nanoparticle monolayer array formed on the gallium arsenide …
FIG. 6 is a cross-sectional view illustrating a process for removing polystyrene according to an exemplary embodiment of the present invention. [0067]
FIG. 7 is a scanning electron microscope (SEM) photograph of the porous metal mesh 40 fabricated according to an exemplary embodiment of the present invention. …
FIG. 8 is a schematic view illustrating a method for fabricating the gallium arsenide semiconductor nanowires 60 using the porous metal mesh 40 according to an …
FIG. 9 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (100) gallium arsenide …
FIG. 10 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (111) gallium arsenide …
FIG. 11 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching a p-type (100) gallium arsenide …
FIG. 12 is an SEM photograph of a gallium arsenide semiconductor nanowire 60 array in a zigzag form fabricated by the porous metal mesh 40 at the time of …
FIG. 13 is an SEM photograph of the vertically-aligned gallium arsenide semiconductor nanowire 60 array having the porous surface, fabricated by the method …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a group I II -V compound semiconductor nanowire array, comprising: (a) preparing a patterned palladium containing metal mesh on a surface of a group I II -V compound semiconductor substrate; and (b) wet-etching the I II -V compound semiconductor substrate contacting the metal mesh in an etchant by applying an external bias for electrochemical etching to the metal mesh, wherein a voltage or a current is applied to the metal mesh forming an anode and the substrate contacting the anode is etched which lowers the metal mesh, and wherein a portion of the substrate that does not contact the anode is not etched forming a mesh shape. Currently amended
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein the metal mesh is formed of an alloy of two or more elements or is formed of two or more metals deposited as multiple layers. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein a length of a nanowire is controlled by a time in which the wet-etching is performed or is controlled by a magnitude of the applied bias. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein the etchant includes hydrofluoric acid (HF), hydrochloric acid (HCl), or nitric acid (HNO₃). Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, a nanowire is fabricated to be vertical to the substrate or is fabricated in a zigzag form. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, the bias is applied to the substrate to induce a nanowire to have a porous surface. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, a diameter of a nanowire is adjusted depending on a change in a size of a hole of the metal mesh. Previously presented
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein a group I II -V compound semiconductor is a gallium arsenide. Previously presented
2-3. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
vertically-aligned III-V compound semiconductor nanowire array
Materials described outside the worked examples.
gallium arsenide
GaAs
palladium-containing metal mesh
group III-V compound semiconductor
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a scanning electron microscope (SEM) photograph of the porous metal mesh 40 fabricated according to an exemplary embodiment of the present invention. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0.2–10 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,147,789Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flow chart illustrating a method for fabricating a gallium arsenide semiconductor nanowire array according to an exemplary embodiment of the present …
FIG. 2. Then, as illustrated in
FIG. 3 is a cross-sectional view illustrating a method for transferring the polystyrene nanoparticle monolayer array onto a surface of a gallium arsenide …
FIG. 4, diameters of polystyrene nanoparticles should be decreased through oxygen plasma treatment of the polystyrene nanoparticle monolayer array transferred …
FIG. 5 is a cross-sectional view illustrating a metal thin film deposited on the polystyrene nanoparticle monolayer array formed on the gallium arsenide …
FIG. 6 is a cross-sectional view illustrating a process for removing polystyrene according to an exemplary embodiment of the present invention. [0067]
FIG. 7 is a scanning electron microscope (SEM) photograph of the porous metal mesh 40 fabricated according to an exemplary embodiment of the present invention. …
FIG. 8 is a schematic view illustrating a method for fabricating the gallium arsenide semiconductor nanowires 60 using the porous metal mesh 40 according to an …
FIG. 9 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (100) gallium arsenide …
FIG. 10 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (111) gallium arsenide …
FIG. 11 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching a p-type (100) gallium arsenide …
FIG. 12 is an SEM photograph of a gallium arsenide semiconductor nanowire 60 array in a zigzag form fabricated by the porous metal mesh 40 at the time of …
FIG. 13 is an SEM photograph of the vertically-aligned gallium arsenide semiconductor nanowire 60 array having the porous surface, fabricated by the method …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a group I II -V compound semiconductor nanowire array, comprising: (a) preparing a patterned palladium containing metal mesh on a surface of a group I II -V compound semiconductor substrate; and (b) wet-etching the I II -V compound semiconductor substrate contacting the metal mesh in an etchant by applying an external bias for electrochemical etching to the metal mesh, wherein a voltage or a current is applied to the metal mesh forming an anode and the substrate contacting the anode is etched which lowers the metal mesh, and wherein a portion of the substrate that does not contact the anode is not etched forming a mesh shape. Currently amended
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein the metal mesh is formed of an alloy of two or more elements or is formed of two or more metals deposited as multiple layers. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein a length of a nanowire is controlled by a time in which the wet-etching is performed or is controlled by a magnitude of the applied bias. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein the etchant includes hydrofluoric acid (HF), hydrochloric acid (HCl), or nitric acid (HNO₃). Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, a nanowire is fabricated to be vertical to the substrate or is fabricated in a zigzag form. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, the bias is applied to the substrate to induce a nanowire to have a porous surface. Original
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, a diameter of a nanowire is adjusted depending on a change in a size of a hole of the metal mesh. Previously presented
The method for fabricating a group I II -V compound semiconductor nanowire array of claim 1, wherein a group I II -V compound semiconductor is a gallium arsenide. Previously presented
2-3. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
vertically-aligned III-V compound semiconductor nanowire array
Materials described outside the worked examples.
gallium arsenide
GaAs
palladium-containing metal mesh
group III-V compound semiconductor
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a scanning electron microscope (SEM) photograph of the porous metal mesh 40 fabricated according to an exemplary embodiment of the present invention. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0.2–10 V | — |
Related documents with shared materials, methods, properties, or citations.
hydrofluoric acid
HF
hydrochloric acid
HCl
nitric acid
HNO₃
silver
Ag
gold
Au
palladium
Pd
platinum
Pt
FIG. 9 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (100) gallium arsenide …
FIG. 10 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (111) gallium arsenide …
FIG. 11 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching a p-type (100) gallium arsenide …
FIG. 12 is an SEM photograph of a gallium arsenide semiconductor nanowire 60 array in a zigzag form fabricated by the porous metal mesh 40 at the time of …
FIG. 13 is an SEM photograph of the vertically-aligned gallium arsenide semiconductor nanowire 60 array having the porous surface, fabricated by the method …
hydrofluoric acid
HF
hydrochloric acid
HCl
nitric acid
HNO₃
silver
Ag
gold
Au
palladium
Pd
platinum
Pt
FIG. 9 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (100) gallium arsenide …
FIG. 10 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (111) gallium arsenide …
FIG. 11 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching a p-type (100) gallium arsenide …
FIG. 12 is an SEM photograph of a gallium arsenide semiconductor nanowire 60 array in a zigzag form fabricated by the porous metal mesh 40 at the time of …
FIG. 13 is an SEM photograph of the vertically-aligned gallium arsenide semiconductor nanowire 60 array having the porous surface, fabricated by the method …
hydrofluoric acid
HF
hydrochloric acid
HCl
nitric acid
HNO₃
silver
Ag
gold
Au
palladium
Pd
platinum
Pt
FIG. 9 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (100) gallium arsenide …
FIG. 10 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (111) gallium arsenide …
FIG. 11 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching a p-type (100) gallium arsenide …
FIG. 12 is an SEM photograph of a gallium arsenide semiconductor nanowire 60 array in a zigzag form fabricated by the porous metal mesh 40 at the time of …
FIG. 13 is an SEM photograph of the vertically-aligned gallium arsenide semiconductor nanowire 60 array having the porous surface, fabricated by the method …
hydrofluoric acid
HF
hydrochloric acid
HCl
nitric acid
HNO₃
silver
Ag
gold
Au
palladium
Pd
platinum
Pt
FIG. 9 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (100) gallium arsenide …
FIG. 10 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching an n-type (111) gallium arsenide …
FIG. 11 is an SEM photograph of a vertically-aligned gallium arsenide semiconductor nanowire 60 array formed by wet-etching a p-type (100) gallium arsenide …
FIG. 12 is an SEM photograph of a gallium arsenide semiconductor nanowire 60 array in a zigzag form fabricated by the porous metal mesh 40 at the time of …
FIG. 13 is an SEM photograph of the vertically-aligned gallium arsenide semiconductor nanowire 60 array having the porous surface, fabricated by the method …