Patent
US 9,525,413POWER SWITCHING SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS AND DRIVER CIRCUITRY
John ROBERTS
US
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Patent
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Patent
US 9,525,413Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN transistor switching device comprising: an enhancement mode (E-Mode) GaN switch having an integrated GaN driver; the E-Mode GaN switch comprising a GaN transistor switch D₃ fabricated on a substrate 5 and the integrated GaN driver being integrated monolithically with the GaN transistor switch D₃ on the substrate, wherein: the integrated GaN driver comprises a first, pull-up, E-Mode GaN driver transistor D 1 and a second, pull-down, E-Mode GaN driver transistor D2, the drain of the D 1 being coupled to V c c, and the source of D 1 being coupled to the drain of D₂ at a node N, and node N 10 being coupled to the gate of D3, and an internal source-sense connection closely coupling the source of D₃ and the source of D2, such that the first transistor D 1 operates to deliver a drive voltage to the gate of the GaN transistor switch D3, and the second transistor D₂ operates to clamp the gate of the GaN transistor switch D₃ to Vss by means of the internal source-sense connection SS ntemi; 15 inputs for coupling to a pre-driver supplying gate drive voltages to the gates of D₁ and D₂ and, optionally, to the gate of D3, and an external source-sense connection SS exteai for coupling to the pre-driver.
The device of claim 1 wherein D₃ is a large gate width E-Mode GaN H EMT having a threshold voltage of-1.5V and D 1 and D₂ are smaller gate width E-Mode GaN H EMTs.
A method of operating the GaN switching device D₃ having integrated GaN driver circuitry comprising D 1 and D2, as defined in claim 1, comprising: providing, from a pre-driver, dual voltage drive outputs comprising a first drive voltage 0-Vcc i for driving the gate of D₁ and a second drive voltage 0-V cc 2 for driving the gate of D2, wherein Vcc i is greater than V c c2.
A GaN power switching system comprising: an enhancement mode (E-Mode) GaN switch and driver circuitry comprising an integrated GaN driver and a discrete pre-driver; the E-Mode GaN switch comprising a GaN transistor switch (D 3) fabricated on a first substrate and the integrated GaN driver being integrated monolithically with the GaN 25 transistor D₃ on the GaN chip, wherein: 18 the integrated GaN driver comprises a first, pull-up, E-mode GaN driver transistor D 1 and a second, pull-down, E-mode GaN driver transistor D2, the drain of D 1 being coupled to the supply voltage V c c, and the source of D 1 being coupled to the drain of D₂ at node N, which is coupled to the gate of D3, such that the first transistor D 1 operates to deliver a 5 drive voltage to the gate of the GaN transistor switch D3, and an internal source-sense connection closely coupling the source of D₃ and the source of D2, such that the second transistor D₂ operates to clamp the gate of the GaN transistor switch D₃ to source by means of the internal source-sense connection SS ntemai; external gate inputs for supplying gate drive voltages from the pre-driver to each of the 10 gates of D 1 and D2, and optionally to the gate of D3; and an external source-sense connection SS exteai for coupling to the pre-driver circuit; and the pre-driver is fabricated on a second, predriver, substrate 102, the pre-driver having an input for receiving an input voltage Vin and outputs for delivering gate drive voltages to the gate connections of each of GaN driver transistors D 1 and D₂ of the integrated GaN 15 driver.
The system of claim 3, wherein the pre-driver further comprises an output for delivering a gate drive voltage to the gate of D3.
The system of claim 3, wherein D₃ is a large gate width E-Mode GaN H EMT having a threshold voltage o f -1.5 V and D 1 and D₂ are smaller gate width E-Mode GaN H EMTs.
The system of claim 3 wherein the pre-driver comprises first, second and third discrete predriver components Pdl, Pd₂ and Pd₃ coupled in parallel paths between the input for 5 Vin and respective outputs for gate voltages to D 1, D₂ and D 3; Pdl and Pd₂ being non-inverting and configured so that when Vin is high a gate drive voltage is supplied to turn on the driver transistor D 1 which provides a gate voltage to the gate of D₃ to turn on the power switch D3, and Pd₃ being an inverting element configured so that when Vin is low a gate drive voltage is supplied to D₂ to turn on D₂ to clamp the power switch D₃ off.
The system of claim 3 wherein the pre-driver provides a single supply voltage V cc, 15 first, second and third pre-driver circuit components Pdl, Pd₂ and Pd3, and a large p-channel MOSFET M 1, wherein the source of the M 1 is coupled to V c c, the drain of the MOSFET M 1 coupled to the gate of D₃ for pulling the gate to the power supply voltage Vc c; Pdl being a non-inverting driver being coupled between the input for Vin and output to the gate of D 1 for driving the gate of D 1; Pd₃ being an inverting driver being coupled 20 between the input for Vin and output to the gate of D₂ for driving the gate of D 2; and Pd₂ being an inverting driver coupled between the input for Vin and the gate of the p-channel MOSFET M 1 for driving the gate of M 1, such that M 1 drives the gate of D3.
The system of any claim 3 wherein the pre-driver comprises an integrated circuit using a single supply voltage V c c; first, second and third integrated pre-driver circuit elements 25 Pd l, Pd₂ and Pd3, and a large p-channel MOSFET structure M 1, wherein the source of the M₁ is coupled to V c c, the drain of the MOSFET is coupled to the gate of D₃ for pulling the gate to the power supply voltage V c c; Pdl being a non-inverting driver being coupled between the input for Vin and output to the gate of D 1 for driving the gate of D 1; Pd₃ being an inverting driver being coupled between the input for Vin and output to the gate of D₂ for 20 driving the gate of D 2; and Pd₂ being an inverting driver coupled between the input for Vin and the gate of the p-channel MOSFET M 1, such that M 1 drives the gate of M 1.
The system of claim 3 wherein the pre-driver comprises voltage boost circuitry for developing a supply voltage Vcc i from a supply voltage V c c, wherein Vcc i > V c c; and 5 wherein the predriver is configured to provide a first output drive voltage of 0-Vcc i to the gate of D₁ and a second output voltage 0-Vcc to the gate of D2.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor switching device with integrated GaN driver
GaN power switching system with integrated GaN driver and discrete pre-driver
Materials described outside the worked examples.
E-Mode GaN HEMT
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Threshold Voltage | -1.5 V | E-Mode GaN HEMT |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,525,413Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN transistor switching device comprising: an enhancement mode (E-Mode) GaN switch having an integrated GaN driver; the E-Mode GaN switch comprising a GaN transistor switch D₃ fabricated on a substrate 5 and the integrated GaN driver being integrated monolithically with the GaN transistor switch D₃ on the substrate, wherein: the integrated GaN driver comprises a first, pull-up, E-Mode GaN driver transistor D 1 and a second, pull-down, E-Mode GaN driver transistor D2, the drain of the D 1 being coupled to V c c, and the source of D 1 being coupled to the drain of D₂ at a node N, and node N 10 being coupled to the gate of D3, and an internal source-sense connection closely coupling the source of D₃ and the source of D2, such that the first transistor D 1 operates to deliver a drive voltage to the gate of the GaN transistor switch D3, and the second transistor D₂ operates to clamp the gate of the GaN transistor switch D₃ to Vss by means of the internal source-sense connection SS ntemi; 15 inputs for coupling to a pre-driver supplying gate drive voltages to the gates of D₁ and D₂ and, optionally, to the gate of D3, and an external source-sense connection SS exteai for coupling to the pre-driver.
The device of claim 1 wherein D₃ is a large gate width E-Mode GaN H EMT having a threshold voltage of-1.5V and D 1 and D₂ are smaller gate width E-Mode GaN H EMTs.
A method of operating the GaN switching device D₃ having integrated GaN driver circuitry comprising D 1 and D2, as defined in claim 1, comprising: providing, from a pre-driver, dual voltage drive outputs comprising a first drive voltage 0-Vcc i for driving the gate of D₁ and a second drive voltage 0-V cc 2 for driving the gate of D2, wherein Vcc i is greater than V c c2.
A GaN power switching system comprising: an enhancement mode (E-Mode) GaN switch and driver circuitry comprising an integrated GaN driver and a discrete pre-driver; the E-Mode GaN switch comprising a GaN transistor switch (D 3) fabricated on a first substrate and the integrated GaN driver being integrated monolithically with the GaN 25 transistor D₃ on the GaN chip, wherein: 18 the integrated GaN driver comprises a first, pull-up, E-mode GaN driver transistor D 1 and a second, pull-down, E-mode GaN driver transistor D2, the drain of D 1 being coupled to the supply voltage V c c, and the source of D 1 being coupled to the drain of D₂ at node N, which is coupled to the gate of D3, such that the first transistor D 1 operates to deliver a 5 drive voltage to the gate of the GaN transistor switch D3, and an internal source-sense connection closely coupling the source of D₃ and the source of D2, such that the second transistor D₂ operates to clamp the gate of the GaN transistor switch D₃ to source by means of the internal source-sense connection SS ntemai; external gate inputs for supplying gate drive voltages from the pre-driver to each of the 10 gates of D 1 and D2, and optionally to the gate of D3; and an external source-sense connection SS exteai for coupling to the pre-driver circuit; and the pre-driver is fabricated on a second, predriver, substrate 102, the pre-driver having an input for receiving an input voltage Vin and outputs for delivering gate drive voltages to the gate connections of each of GaN driver transistors D 1 and D₂ of the integrated GaN 15 driver.
The system of claim 3, wherein the pre-driver further comprises an output for delivering a gate drive voltage to the gate of D3.
The system of claim 3, wherein D₃ is a large gate width E-Mode GaN H EMT having a threshold voltage o f -1.5 V and D 1 and D₂ are smaller gate width E-Mode GaN H EMTs.
The system of claim 3 wherein the pre-driver comprises first, second and third discrete predriver components Pdl, Pd₂ and Pd₃ coupled in parallel paths between the input for 5 Vin and respective outputs for gate voltages to D 1, D₂ and D 3; Pdl and Pd₂ being non-inverting and configured so that when Vin is high a gate drive voltage is supplied to turn on the driver transistor D 1 which provides a gate voltage to the gate of D₃ to turn on the power switch D3, and Pd₃ being an inverting element configured so that when Vin is low a gate drive voltage is supplied to D₂ to turn on D₂ to clamp the power switch D₃ off.
The system of claim 3 wherein the pre-driver provides a single supply voltage V cc, 15 first, second and third pre-driver circuit components Pdl, Pd₂ and Pd3, and a large p-channel MOSFET M 1, wherein the source of the M 1 is coupled to V c c, the drain of the MOSFET M 1 coupled to the gate of D₃ for pulling the gate to the power supply voltage Vc c; Pdl being a non-inverting driver being coupled between the input for Vin and output to the gate of D 1 for driving the gate of D 1; Pd₃ being an inverting driver being coupled 20 between the input for Vin and output to the gate of D₂ for driving the gate of D 2; and Pd₂ being an inverting driver coupled between the input for Vin and the gate of the p-channel MOSFET M 1 for driving the gate of M 1, such that M 1 drives the gate of D3.
The system of any claim 3 wherein the pre-driver comprises an integrated circuit using a single supply voltage V c c; first, second and third integrated pre-driver circuit elements 25 Pd l, Pd₂ and Pd3, and a large p-channel MOSFET structure M 1, wherein the source of the M₁ is coupled to V c c, the drain of the MOSFET is coupled to the gate of D₃ for pulling the gate to the power supply voltage V c c; Pdl being a non-inverting driver being coupled between the input for Vin and output to the gate of D 1 for driving the gate of D 1; Pd₃ being an inverting driver being coupled between the input for Vin and output to the gate of D₂ for 20 driving the gate of D 2; and Pd₂ being an inverting driver coupled between the input for Vin and the gate of the p-channel MOSFET M 1, such that M 1 drives the gate of M 1.
The system of claim 3 wherein the pre-driver comprises voltage boost circuitry for developing a supply voltage Vcc i from a supply voltage V c c, wherein Vcc i > V c c; and 5 wherein the predriver is configured to provide a first output drive voltage of 0-Vcc i to the gate of D₁ and a second output voltage 0-Vcc to the gate of D2.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor switching device with integrated GaN driver
GaN power switching system with integrated GaN driver and discrete pre-driver
Materials described outside the worked examples.
E-Mode GaN HEMT
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Threshold Voltage | -1.5 V | E-Mode GaN HEMT |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,525,413Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN transistor switching device comprising: an enhancement mode (E-Mode) GaN switch having an integrated GaN driver; the E-Mode GaN switch comprising a GaN transistor switch D₃ fabricated on a substrate 5 and the integrated GaN driver being integrated monolithically with the GaN transistor switch D₃ on the substrate, wherein: the integrated GaN driver comprises a first, pull-up, E-Mode GaN driver transistor D 1 and a second, pull-down, E-Mode GaN driver transistor D2, the drain of the D 1 being coupled to V c c, and the source of D 1 being coupled to the drain of D₂ at a node N, and node N 10 being coupled to the gate of D3, and an internal source-sense connection closely coupling the source of D₃ and the source of D2, such that the first transistor D 1 operates to deliver a drive voltage to the gate of the GaN transistor switch D3, and the second transistor D₂ operates to clamp the gate of the GaN transistor switch D₃ to Vss by means of the internal source-sense connection SS ntemi; 15 inputs for coupling to a pre-driver supplying gate drive voltages to the gates of D₁ and D₂ and, optionally, to the gate of D3, and an external source-sense connection SS exteai for coupling to the pre-driver.
The device of claim 1 wherein D₃ is a large gate width E-Mode GaN H EMT having a threshold voltage of-1.5V and D 1 and D₂ are smaller gate width E-Mode GaN H EMTs.
A method of operating the GaN switching device D₃ having integrated GaN driver circuitry comprising D 1 and D2, as defined in claim 1, comprising: providing, from a pre-driver, dual voltage drive outputs comprising a first drive voltage 0-Vcc i for driving the gate of D₁ and a second drive voltage 0-V cc 2 for driving the gate of D2, wherein Vcc i is greater than V c c2.
A GaN power switching system comprising: an enhancement mode (E-Mode) GaN switch and driver circuitry comprising an integrated GaN driver and a discrete pre-driver; the E-Mode GaN switch comprising a GaN transistor switch (D 3) fabricated on a first substrate and the integrated GaN driver being integrated monolithically with the GaN 25 transistor D₃ on the GaN chip, wherein: 18 the integrated GaN driver comprises a first, pull-up, E-mode GaN driver transistor D 1 and a second, pull-down, E-mode GaN driver transistor D2, the drain of D 1 being coupled to the supply voltage V c c, and the source of D 1 being coupled to the drain of D₂ at node N, which is coupled to the gate of D3, such that the first transistor D 1 operates to deliver a 5 drive voltage to the gate of the GaN transistor switch D3, and an internal source-sense connection closely coupling the source of D₃ and the source of D2, such that the second transistor D₂ operates to clamp the gate of the GaN transistor switch D₃ to source by means of the internal source-sense connection SS ntemai; external gate inputs for supplying gate drive voltages from the pre-driver to each of the 10 gates of D 1 and D2, and optionally to the gate of D3; and an external source-sense connection SS exteai for coupling to the pre-driver circuit; and the pre-driver is fabricated on a second, predriver, substrate 102, the pre-driver having an input for receiving an input voltage Vin and outputs for delivering gate drive voltages to the gate connections of each of GaN driver transistors D 1 and D₂ of the integrated GaN 15 driver.
The system of claim 3, wherein the pre-driver further comprises an output for delivering a gate drive voltage to the gate of D3.
The system of claim 3, wherein D₃ is a large gate width E-Mode GaN H EMT having a threshold voltage o f -1.5 V and D 1 and D₂ are smaller gate width E-Mode GaN H EMTs.
The system of claim 3 wherein the pre-driver comprises first, second and third discrete predriver components Pdl, Pd₂ and Pd₃ coupled in parallel paths between the input for 5 Vin and respective outputs for gate voltages to D 1, D₂ and D 3; Pdl and Pd₂ being non-inverting and configured so that when Vin is high a gate drive voltage is supplied to turn on the driver transistor D 1 which provides a gate voltage to the gate of D₃ to turn on the power switch D3, and Pd₃ being an inverting element configured so that when Vin is low a gate drive voltage is supplied to D₂ to turn on D₂ to clamp the power switch D₃ off.
The system of claim 3 wherein the pre-driver provides a single supply voltage V cc, 15 first, second and third pre-driver circuit components Pdl, Pd₂ and Pd3, and a large p-channel MOSFET M 1, wherein the source of the M 1 is coupled to V c c, the drain of the MOSFET M 1 coupled to the gate of D₃ for pulling the gate to the power supply voltage Vc c; Pdl being a non-inverting driver being coupled between the input for Vin and output to the gate of D 1 for driving the gate of D 1; Pd₃ being an inverting driver being coupled 20 between the input for Vin and output to the gate of D₂ for driving the gate of D 2; and Pd₂ being an inverting driver coupled between the input for Vin and the gate of the p-channel MOSFET M 1 for driving the gate of M 1, such that M 1 drives the gate of D3.
The system of any claim 3 wherein the pre-driver comprises an integrated circuit using a single supply voltage V c c; first, second and third integrated pre-driver circuit elements 25 Pd l, Pd₂ and Pd3, and a large p-channel MOSFET structure M 1, wherein the source of the M₁ is coupled to V c c, the drain of the MOSFET is coupled to the gate of D₃ for pulling the gate to the power supply voltage V c c; Pdl being a non-inverting driver being coupled between the input for Vin and output to the gate of D 1 for driving the gate of D 1; Pd₃ being an inverting driver being coupled between the input for Vin and output to the gate of D₂ for 20 driving the gate of D 2; and Pd₂ being an inverting driver coupled between the input for Vin and the gate of the p-channel MOSFET M 1, such that M 1 drives the gate of M 1.
The system of claim 3 wherein the pre-driver comprises voltage boost circuitry for developing a supply voltage Vcc i from a supply voltage V c c, wherein Vcc i > V c c; and 5 wherein the predriver is configured to provide a first output drive voltage of 0-Vcc i to the gate of D₁ and a second output voltage 0-Vcc to the gate of D2.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor switching device with integrated GaN driver
GaN power switching system with integrated GaN driver and discrete pre-driver
Materials described outside the worked examples.
E-Mode GaN HEMT
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Threshold Voltage | -1.5 V | E-Mode GaN HEMT |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,525,413Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN transistor switching device comprising: an enhancement mode (E-Mode) GaN switch having an integrated GaN driver; the E-Mode GaN switch comprising a GaN transistor switch D₃ fabricated on a substrate 5 and the integrated GaN driver being integrated monolithically with the GaN transistor switch D₃ on the substrate, wherein: the integrated GaN driver comprises a first, pull-up, E-Mode GaN driver transistor D 1 and a second, pull-down, E-Mode GaN driver transistor D2, the drain of the D 1 being coupled to V c c, and the source of D 1 being coupled to the drain of D₂ at a node N, and node N 10 being coupled to the gate of D3, and an internal source-sense connection closely coupling the source of D₃ and the source of D2, such that the first transistor D 1 operates to deliver a drive voltage to the gate of the GaN transistor switch D3, and the second transistor D₂ operates to clamp the gate of the GaN transistor switch D₃ to Vss by means of the internal source-sense connection SS ntemi; 15 inputs for coupling to a pre-driver supplying gate drive voltages to the gates of D₁ and D₂ and, optionally, to the gate of D3, and an external source-sense connection SS exteai for coupling to the pre-driver.
The device of claim 1 wherein D₃ is a large gate width E-Mode GaN H EMT having a threshold voltage of-1.5V and D 1 and D₂ are smaller gate width E-Mode GaN H EMTs.
A method of operating the GaN switching device D₃ having integrated GaN driver circuitry comprising D 1 and D2, as defined in claim 1, comprising: providing, from a pre-driver, dual voltage drive outputs comprising a first drive voltage 0-Vcc i for driving the gate of D₁ and a second drive voltage 0-V cc 2 for driving the gate of D2, wherein Vcc i is greater than V c c2.
A GaN power switching system comprising: an enhancement mode (E-Mode) GaN switch and driver circuitry comprising an integrated GaN driver and a discrete pre-driver; the E-Mode GaN switch comprising a GaN transistor switch (D 3) fabricated on a first substrate and the integrated GaN driver being integrated monolithically with the GaN 25 transistor D₃ on the GaN chip, wherein: 18 the integrated GaN driver comprises a first, pull-up, E-mode GaN driver transistor D 1 and a second, pull-down, E-mode GaN driver transistor D2, the drain of D 1 being coupled to the supply voltage V c c, and the source of D 1 being coupled to the drain of D₂ at node N, which is coupled to the gate of D3, such that the first transistor D 1 operates to deliver a 5 drive voltage to the gate of the GaN transistor switch D3, and an internal source-sense connection closely coupling the source of D₃ and the source of D2, such that the second transistor D₂ operates to clamp the gate of the GaN transistor switch D₃ to source by means of the internal source-sense connection SS ntemai; external gate inputs for supplying gate drive voltages from the pre-driver to each of the 10 gates of D 1 and D2, and optionally to the gate of D3; and an external source-sense connection SS exteai for coupling to the pre-driver circuit; and the pre-driver is fabricated on a second, predriver, substrate 102, the pre-driver having an input for receiving an input voltage Vin and outputs for delivering gate drive voltages to the gate connections of each of GaN driver transistors D 1 and D₂ of the integrated GaN 15 driver.
The system of claim 3, wherein the pre-driver further comprises an output for delivering a gate drive voltage to the gate of D3.
The system of claim 3, wherein D₃ is a large gate width E-Mode GaN H EMT having a threshold voltage o f -1.5 V and D 1 and D₂ are smaller gate width E-Mode GaN H EMTs.
The system of claim 3 wherein the pre-driver comprises first, second and third discrete predriver components Pdl, Pd₂ and Pd₃ coupled in parallel paths between the input for 5 Vin and respective outputs for gate voltages to D 1, D₂ and D 3; Pdl and Pd₂ being non-inverting and configured so that when Vin is high a gate drive voltage is supplied to turn on the driver transistor D 1 which provides a gate voltage to the gate of D₃ to turn on the power switch D3, and Pd₃ being an inverting element configured so that when Vin is low a gate drive voltage is supplied to D₂ to turn on D₂ to clamp the power switch D₃ off.
The system of claim 3 wherein the pre-driver provides a single supply voltage V cc, 15 first, second and third pre-driver circuit components Pdl, Pd₂ and Pd3, and a large p-channel MOSFET M 1, wherein the source of the M 1 is coupled to V c c, the drain of the MOSFET M 1 coupled to the gate of D₃ for pulling the gate to the power supply voltage Vc c; Pdl being a non-inverting driver being coupled between the input for Vin and output to the gate of D 1 for driving the gate of D 1; Pd₃ being an inverting driver being coupled 20 between the input for Vin and output to the gate of D₂ for driving the gate of D 2; and Pd₂ being an inverting driver coupled between the input for Vin and the gate of the p-channel MOSFET M 1 for driving the gate of M 1, such that M 1 drives the gate of D3.
The system of any claim 3 wherein the pre-driver comprises an integrated circuit using a single supply voltage V c c; first, second and third integrated pre-driver circuit elements 25 Pd l, Pd₂ and Pd3, and a large p-channel MOSFET structure M 1, wherein the source of the M₁ is coupled to V c c, the drain of the MOSFET is coupled to the gate of D₃ for pulling the gate to the power supply voltage V c c; Pdl being a non-inverting driver being coupled between the input for Vin and output to the gate of D 1 for driving the gate of D 1; Pd₃ being an inverting driver being coupled between the input for Vin and output to the gate of D₂ for 20 driving the gate of D 2; and Pd₂ being an inverting driver coupled between the input for Vin and the gate of the p-channel MOSFET M 1, such that M 1 drives the gate of M 1.
The system of claim 3 wherein the pre-driver comprises voltage boost circuitry for developing a supply voltage Vcc i from a supply voltage V c c, wherein Vcc i > V c c; and 5 wherein the predriver is configured to provide a first output drive voltage of 0-Vcc i to the gate of D₁ and a second output voltage 0-Vcc to the gate of D2.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor switching device with integrated GaN driver
GaN power switching system with integrated GaN driver and discrete pre-driver
Materials described outside the worked examples.
E-Mode GaN HEMT
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Threshold Voltage | -1.5 V | E-Mode GaN HEMT |
Related documents with shared materials, methods, properties, or citations.
| 0–6 V |
| — |
Temperature | ≤ 20 k | — |
Voltage | ≥ 1 V | — |
Voltage | 0–10 V | — |
Thickness | ≥ 1 mm | — |
WAFER LEVEL PACKAGED GAN POWER SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF
| 0–6 V |
| — |
Temperature | ≤ 20 k | — |
Voltage | ≥ 1 V | — |
Voltage | 0–10 V | — |
Thickness | ≥ 1 mm | — |
WAFER LEVEL PACKAGED GAN POWER SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF
| 0–6 V |
| — |
Temperature | ≤ 20 k | — |
Voltage | ≥ 1 V | — |
Voltage | 0–10 V | — |
Thickness | ≥ 1 mm | — |
WAFER LEVEL PACKAGED GAN POWER SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF
| 0–6 V |
| — |
Temperature | ≤ 20 k | — |
Voltage | ≥ 1 V | — |
Voltage | 0–10 V | — |
Thickness | ≥ 1 mm | — |
WAFER LEVEL PACKAGED GAN POWER SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF