Patent
US 11,417,529PLASMA-BASED EDGE TERMINATIONS FOR GALLIUM NITRIDE POWER DEVICES
Yuji Zhao
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,417,529Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 C depicts ICP/RTA treated vertical GaN p-n diode 120 after rapid thermal annealing (RTA) (e.g., at 400 ° C) of ICP treated vertical GaN p-n diode 118. …
FIG. 2B shows the current conduction path cut off in hydrogenated p-GaN. [0020]
FIG. 3B depicts a cross-section of a device with guard rings (GRs).
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of treating a G aN power device comprising a p- GaN layer, the method comprising: covering a portion of the p- G aN layer with a metal layer; exposing the p- G aN layer to a hydrogen plasma; thermally annealing the p- G aN layer, thereby passivating a region of the p- G aN layer proximate the metal layer; and covering an additional portion of the p- G aN layer with an additional metal layer separated from the metal layer on a surface of the p- G aN layer, wherein thermally annealing the p- G aN layer comprises passivating a region of the p- G aN la y er between the metal la y er and the additional metal la y er. Currently amended
The method of claim 1, wherein thermally annealing the p- GaN layer comprises heating the p-G aN layer to a temperature in a range between 350 0 C and 500 0 C. Currently amended
The method of claim 1, wherein passivating the p- G aN layer comprises passivating all of the p- G aN layer into highly resistant- G aN (HR- G aN). Currently amended
The method of claim 1 [[5]], wherein the metal layer is in the form of a metal circle, and the additional metal layer is a metal ring surrounding the circle. Currently amended
The method of claim 1, wherein the GaN power device comprises a GaN p-n diode. Original
Canceled
12-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN p-n diode
Materials described outside the worked examples.
p-GaN
GaN
metal layer (anode/electrode)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
specific on-resistance (Rsp) | 0.4 mΩ·cm² | GaN |
breakdown voltage (BV) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,417,529Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 C depicts ICP/RTA treated vertical GaN p-n diode 120 after rapid thermal annealing (RTA) (e.g., at 400 ° C) of ICP treated vertical GaN p-n diode 118. …
FIG. 2B shows the current conduction path cut off in hydrogenated p-GaN. [0020]
FIG. 3B depicts a cross-section of a device with guard rings (GRs).
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of treating a G aN power device comprising a p- GaN layer, the method comprising: covering a portion of the p- G aN layer with a metal layer; exposing the p- G aN layer to a hydrogen plasma; thermally annealing the p- G aN layer, thereby passivating a region of the p- G aN layer proximate the metal layer; and covering an additional portion of the p- G aN layer with an additional metal layer separated from the metal layer on a surface of the p- G aN layer, wherein thermally annealing the p- G aN layer comprises passivating a region of the p- G aN la y er between the metal la y er and the additional metal la y er. Currently amended
The method of claim 1, wherein thermally annealing the p- GaN layer comprises heating the p-G aN layer to a temperature in a range between 350 0 C and 500 0 C. Currently amended
The method of claim 1, wherein passivating the p- G aN layer comprises passivating all of the p- G aN layer into highly resistant- G aN (HR- G aN). Currently amended
The method of claim 1 [[5]], wherein the metal layer is in the form of a metal circle, and the additional metal layer is a metal ring surrounding the circle. Currently amended
The method of claim 1, wherein the GaN power device comprises a GaN p-n diode. Original
Canceled
12-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN p-n diode
Materials described outside the worked examples.
p-GaN
GaN
metal layer (anode/electrode)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
specific on-resistance (Rsp) | 0.4 mΩ·cm² | GaN |
breakdown voltage (BV) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,417,529Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 C depicts ICP/RTA treated vertical GaN p-n diode 120 after rapid thermal annealing (RTA) (e.g., at 400 ° C) of ICP treated vertical GaN p-n diode 118. …
FIG. 2B shows the current conduction path cut off in hydrogenated p-GaN. [0020]
FIG. 3B depicts a cross-section of a device with guard rings (GRs).
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of treating a G aN power device comprising a p- GaN layer, the method comprising: covering a portion of the p- G aN layer with a metal layer; exposing the p- G aN layer to a hydrogen plasma; thermally annealing the p- G aN layer, thereby passivating a region of the p- G aN layer proximate the metal layer; and covering an additional portion of the p- G aN layer with an additional metal layer separated from the metal layer on a surface of the p- G aN layer, wherein thermally annealing the p- G aN layer comprises passivating a region of the p- G aN la y er between the metal la y er and the additional metal la y er. Currently amended
The method of claim 1, wherein thermally annealing the p- GaN layer comprises heating the p-G aN layer to a temperature in a range between 350 0 C and 500 0 C. Currently amended
The method of claim 1, wherein passivating the p- G aN layer comprises passivating all of the p- G aN layer into highly resistant- G aN (HR- G aN). Currently amended
The method of claim 1 [[5]], wherein the metal layer is in the form of a metal circle, and the additional metal layer is a metal ring surrounding the circle. Currently amended
The method of claim 1, wherein the GaN power device comprises a GaN p-n diode. Original
Canceled
12-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN p-n diode
Materials described outside the worked examples.
p-GaN
GaN
metal layer (anode/electrode)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
specific on-resistance (Rsp) | 0.4 mΩ·cm² | GaN |
breakdown voltage (BV) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,417,529Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 C depicts ICP/RTA treated vertical GaN p-n diode 120 after rapid thermal annealing (RTA) (e.g., at 400 ° C) of ICP treated vertical GaN p-n diode 118. …
FIG. 2B shows the current conduction path cut off in hydrogenated p-GaN. [0020]
FIG. 3B depicts a cross-section of a device with guard rings (GRs).
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of treating a G aN power device comprising a p- GaN layer, the method comprising: covering a portion of the p- G aN layer with a metal layer; exposing the p- G aN layer to a hydrogen plasma; thermally annealing the p- G aN layer, thereby passivating a region of the p- G aN layer proximate the metal layer; and covering an additional portion of the p- G aN layer with an additional metal layer separated from the metal layer on a surface of the p- G aN layer, wherein thermally annealing the p- G aN layer comprises passivating a region of the p- G aN la y er between the metal la y er and the additional metal la y er. Currently amended
The method of claim 1, wherein thermally annealing the p- GaN layer comprises heating the p-G aN layer to a temperature in a range between 350 0 C and 500 0 C. Currently amended
The method of claim 1, wherein passivating the p- G aN layer comprises passivating all of the p- G aN layer into highly resistant- G aN (HR- G aN). Currently amended
The method of claim 1 [[5]], wherein the metal layer is in the form of a metal circle, and the additional metal layer is a metal ring surrounding the circle. Currently amended
The method of claim 1, wherein the GaN power device comprises a GaN p-n diode. Original
Canceled
12-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN p-n diode
Materials described outside the worked examples.
p-GaN
GaN
metal layer (anode/electrode)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
specific on-resistance (Rsp) | 0.4 mΩ·cm² | GaN |
breakdown voltage (BV) |
Related documents with shared materials, methods, properties, or citations.
hydrogen plasma
H₂
Pd/Ni/Au
Ti/Al/Ti/Au
| -1400 V |
GaN |
on/off ratio | 10000000000 | GaN |
turn-on voltage | 3.56 V | GaN |
on-resistance (Ron) with guard rings | 0.65 mΩ·cm² | GaN |
breakdown voltage (BV) with 10 guard rings | 1700 V | GaN |
Temperature | 350–500 °C | — |
hydrogen plasma
H₂
Pd/Ni/Au
Ti/Al/Ti/Au
| -1400 V |
GaN |
on/off ratio | 10000000000 | GaN |
turn-on voltage | 3.56 V | GaN |
on-resistance (Ron) with guard rings | 0.65 mΩ·cm² | GaN |
breakdown voltage (BV) with 10 guard rings | 1700 V | GaN |
Temperature | 350–500 °C | — |
hydrogen plasma
H₂
Pd/Ni/Au
Ti/Al/Ti/Au
| -1400 V |
GaN |
on/off ratio | 10000000000 | GaN |
turn-on voltage | 3.56 V | GaN |
on-resistance (Ron) with guard rings | 0.65 mΩ·cm² | GaN |
breakdown voltage (BV) with 10 guard rings | 1700 V | GaN |
Temperature | 350–500 °C | — |
hydrogen plasma
H₂
Pd/Ni/Au
Ti/Al/Ti/Au
| -1400 V |
GaN |
on/off ratio | 10000000000 | GaN |
turn-on voltage | 3.56 V | GaN |
on-resistance (Ron) with guard rings | 0.65 mΩ·cm² | GaN |
breakdown voltage (BV) with 10 guard rings | 1700 V | GaN |
Temperature | 350–500 °C | — |