Patent
US 11,276,764METHOD OF MAKING HIGH FREQUENCY InGaP/GaAs HBTs
Yuefei Yang
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The device 100 a may further comprise multiple emitter contact layers 124a-124b and corresponding emitter contact metals 130a-130b and either one base …
FIG. 2, a diagram illustrating an example emb diment of the present invention having multi-emitters is shown. A cross-sectional view of the device 100 a is …
FIG. 3. The device 100 c may not implement the collector layer region 108b next to the collector contact metal 126. The passivation layer 110 and the low-k …
FIG. 4. The contact site 220a may be a relatively flat region between the collector layer 108 (e.g., the slope of the base-collector mesa 140) and the collector …
FIG. 5, a diagram illustrating a base-collector mesa etch through a collector layer is shown. A cross-sectional view of the device 100 d is shown. The device …
FIG. 6, a diagram illustrating a base feedline and a base-collector mesa having a positive slope is shown. A cross-sectional view 300a is shown. The …
FIG. 7, a diagram illustrating a base feedline and base-collector mesa having a negative slope is shown. A cross-sectional view 300b is shown. The …
FIG. 8, a diagram illustrating a feedline to an emitter contact is shown. A cross-sectional view 320 is shown. The cross-sectional view 320 may comprise a …
FIG. 9, a diagram illustrating a base contact metal on top of a GaAs base layer by opening an InGaP emitter layer is shown. A view 350a of a portion of an …
FIG. 10, a diagram illustrating a base contact metal on top of an InGaP emitter layer with an alloy through to enable metal to reach a GaAs base layer is …
FIG. 11, a diagram illustrating an interconnect metal to connect an emitter contact metal using a single emitter with an emitter feedline crossing over a …
FIG. 12, a diagram illustrating an interconnect metal with a copper pillar to connect an emitter contact metal using a multi-emitter is shown. A …
FIG. 13, a diagram illustrating an interconnect metal to connect an emitter contact metal using a multi-emitter is shown. A cross- sectional view of the device …
FIG. 14, a diagram illustrating an interconnect metal to connect a merged emitter contact metal using a multi-emitter is shown. A cross-sectional view of the …
FIG. 15, a diagram illustrating an HBT implemented as part of a BiHEMT structure is shown. A cross-sectional view of a structure 480 is shown. The structure …
FIG. 16, a diagram illustrating active layers of an HBT isolated from a base post is shown. A cross-sectional view of the device 100i is shown. The device 100i …
FIG. 17, a method (or process) 580 is shown. The method 580 may illustrate a fabrication of a low-parasitic, high-frequency InGaP/GaAs HBT. The method 580 may …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: a semiconductor die including a plurality of semiconductor layers disposed on a GaAs substrate; a first contact electrically coupled to a semiconductor emitter layer; a second contact electrically coupled to a semiconductor base layer; a third contact electrically coupled to a semiconductor sub-collector layer; a first passivation layer covering one or more of said semiconductor, said first contact, said second contact and said third contact, said first passivation layer comprises an inorganic insulator; a second passivation layer comprising an inorganic insulator or organic polymer with low dielectric constant deposited on said first passivation layer; and an interconnect metal coupled to said first contact and separated from said first passivation layer by said second passivation layer.
The device according to claim 1, further comprising: 2 an emitter mesa to make an island of emitter layers; 3 a base-collector mesa to make an island of base-collector layers; and a subcollector isolation to isolate said semiconductor sub-collector layer, wherein (a) said semiconductor sub-collector layer has a first band-gap, (b) said semiconductor emitter layer has a second band-gap and (c) said semiconductor base layer has a third band-gap.
The device according to claim 1, wherein (i) the device comprises of an integrated HBT and a field effect transistor (FET), (ii) epitaxial layers of the FET are under layers of the HBT and (iii) the FET comprises of a gate, a source, and a drain.
The device according to claim 1, wherein (i) the device comprises of an integrated HBT and a field effect transistor (FET), (ii) epitaxial layers of the FET are on top of layers of the 4 HBT and (iii) the FET comprises of a gate, a source, and a drain.
1 17. The device according to claim 1, wherein said first contact is separated from said second passivation layer by a third passivation layer comprising said inorganic insulator and a fourth passivation layer comprising said organic polymer with said low dielectric constant.
A device comprising: a semiconductor die including a plurality of semiconductor layers disposed on a GaAs substrate; a first contact electrically coupled to a semiconductor emitter layer; a second contact electrically coupled to a semiconductor base layer; a third contact electrically coupled to a semiconductor sub-collector layer; a first passivation layer covering one or more of said semiconductor, said first contact, said second contact and said third contact, said first passivation layer comprises an inorganic insulator; an interconnect metal coupled to said first contact; and an air-gap formed between said first passivation layer and said interconnect metal, wherein said air-gap is formed by (i) depositing a sacrificial material on said first passivation layer 18 and (ii) removing said sacrificial material to leave said air-gap.
1 19. A method for fabricating a transistor comprising the steps of: (A) depositing an emitter contact; (B) forming an emitter mesa by (i) etching off emitter cap layers and (ii) stopping at an InGaP emitter layer; (C) depositing a base contact to connect to a base layer, wherein said base contact is deposited (i) on top of said InGaP emitter layer and then alloyed to said base layer by annealing or (ii) on top of said base layer after etching off said InGaP emitter layer; (D) forming a base-collector mesa by etching off said base layer and partially or entirely etching off a collector layer; (E) depositing a collector contact on a sub-collector layer; (F) forming a sub-collector isolation by one of (i) ion implantation or (ii) a mesa etch; (G) depositing a first passivation layer, wherein said first passivation layer (i) covers said emitter contact, said base contact and said collector contact and (ii) comprises an inorganic insulator; (H) forming a silicon nitride opening on top of said emitter contact, said base contact and said collector contact by 23 dry etching; 24 (I) depositing a second passivation layer on top of said first passivation layer, wherein said second passivation layer comprises an inorganic insulator or organic polymer with low dielectric constant; (J) creating openings for electrical connections in said second passivation layer on top of said emitter contact, said base contact and collector contact; and (K) depositing an interconnect metal coupled to said emitter contact and separated second passivation layer, wherein said interconnect transistor.
The method according to claim 19, further nitride for a metal-insulator-metal capacitor and passivation layer and open via; (N) depositing a passivation layer comprises silicon nitride and said passivation layer and making openings on bond from said first passivation layer by said metal enables a connection to outside said comprising the steps of: (L) depositing silicon open silicon nitride via; (M) applying a third second interconnect metal, wherein said third organic polymer; and (0) forming a fourth pads.
Layer stacks claimed or described, ordered top of device to substrate.
InGaP/GaAs Heterojunction Bipolar Transistor (HBT)
High Electron Mobility Transistor (HEMT)/pseudomorphic HEMT (pHEMT)
No layer stack recorded.
Materials described outside the worked examples.
GaAs substrate
GaAs
inorganic insulator (first passivation layer)
organic polymer with low dielectric constant (second passivation layer)
InGaAs base layer
InGaAs
GaAsSb base layer
GaAsSb
GaInAsN base layer
GaInAsN
InGaP emitter layer
InGaP
AlGaAs emitter layer
AlGaAs
silicon nitride (first passivation layer)
Si₃N₄
Polyimide or BCB (second passivation layer)
polyimide low-k passivation layer
BCB low-k passivation layer
n+ InGaAs/GaAs emitter contact layer
InGaAs/GaAs
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 1 nm | — |
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The device 100 a may further comprise multiple emitter contact layers 124a-124b and corresponding emitter contact metals 130a-130b and either one base …
FIG. 2, a diagram illustrating an example emb diment of the present invention having multi-emitters is shown. A cross-sectional view of the device 100 a is …
FIG. 3. The device 100 c may not implement the collector layer region 108b next to the collector contact metal 126. The passivation layer 110 and the low-k …
FIG. 4. The contact site 220a may be a relatively flat region between the collector layer 108 (e.g., the slope of the base-collector mesa 140) and the collector …
FIG. 5, a diagram illustrating a base-collector mesa etch through a collector layer is shown. A cross-sectional view of the device 100 d is shown. The device …
FIG. 6, a diagram illustrating a base feedline and a base-collector mesa having a positive slope is shown. A cross-sectional view 300a is shown. The …
FIG. 7, a diagram illustrating a base feedline and base-collector mesa having a negative slope is shown. A cross-sectional view 300b is shown. The …
FIG. 8, a diagram illustrating a feedline to an emitter contact is shown. A cross-sectional view 320 is shown. The cross-sectional view 320 may comprise a …
FIG. 9, a diagram illustrating a base contact metal on top of a GaAs base layer by opening an InGaP emitter layer is shown. A view 350a of a portion of an …
FIG. 10, a diagram illustrating a base contact metal on top of an InGaP emitter layer with an alloy through to enable metal to reach a GaAs base layer is …
FIG. 11, a diagram illustrating an interconnect metal to connect an emitter contact metal using a single emitter with an emitter feedline crossing over a …
FIG. 12, a diagram illustrating an interconnect metal with a copper pillar to connect an emitter contact metal using a multi-emitter is shown. A …
FIG. 13, a diagram illustrating an interconnect metal to connect an emitter contact metal using a multi-emitter is shown. A cross- sectional view of the device …
FIG. 14, a diagram illustrating an interconnect metal to connect a merged emitter contact metal using a multi-emitter is shown. A cross-sectional view of the …
FIG. 15, a diagram illustrating an HBT implemented as part of a BiHEMT structure is shown. A cross-sectional view of a structure 480 is shown. The structure …
FIG. 16, a diagram illustrating active layers of an HBT isolated from a base post is shown. A cross-sectional view of the device 100i is shown. The device 100i …
FIG. 17, a method (or process) 580 is shown. The method 580 may illustrate a fabrication of a low-parasitic, high-frequency InGaP/GaAs HBT. The method 580 may …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: a semiconductor die including a plurality of semiconductor layers disposed on a GaAs substrate; a first contact electrically coupled to a semiconductor emitter layer; a second contact electrically coupled to a semiconductor base layer; a third contact electrically coupled to a semiconductor sub-collector layer; a first passivation layer covering one or more of said semiconductor, said first contact, said second contact and said third contact, said first passivation layer comprises an inorganic insulator; a second passivation layer comprising an inorganic insulator or organic polymer with low dielectric constant deposited on said first passivation layer; and an interconnect metal coupled to said first contact and separated from said first passivation layer by said second passivation layer.
The device according to claim 1, further comprising: 2 an emitter mesa to make an island of emitter layers; 3 a base-collector mesa to make an island of base-collector layers; and a subcollector isolation to isolate said semiconductor sub-collector layer, wherein (a) said semiconductor sub-collector layer has a first band-gap, (b) said semiconductor emitter layer has a second band-gap and (c) said semiconductor base layer has a third band-gap.
The device according to claim 1, wherein (i) the device comprises of an integrated HBT and a field effect transistor (FET), (ii) epitaxial layers of the FET are under layers of the HBT and (iii) the FET comprises of a gate, a source, and a drain.
The device according to claim 1, wherein (i) the device comprises of an integrated HBT and a field effect transistor (FET), (ii) epitaxial layers of the FET are on top of layers of the 4 HBT and (iii) the FET comprises of a gate, a source, and a drain.
1 17. The device according to claim 1, wherein said first contact is separated from said second passivation layer by a third passivation layer comprising said inorganic insulator and a fourth passivation layer comprising said organic polymer with said low dielectric constant.
A device comprising: a semiconductor die including a plurality of semiconductor layers disposed on a GaAs substrate; a first contact electrically coupled to a semiconductor emitter layer; a second contact electrically coupled to a semiconductor base layer; a third contact electrically coupled to a semiconductor sub-collector layer; a first passivation layer covering one or more of said semiconductor, said first contact, said second contact and said third contact, said first passivation layer comprises an inorganic insulator; an interconnect metal coupled to said first contact; and an air-gap formed between said first passivation layer and said interconnect metal, wherein said air-gap is formed by (i) depositing a sacrificial material on said first passivation layer 18 and (ii) removing said sacrificial material to leave said air-gap.
1 19. A method for fabricating a transistor comprising the steps of: (A) depositing an emitter contact; (B) forming an emitter mesa by (i) etching off emitter cap layers and (ii) stopping at an InGaP emitter layer; (C) depositing a base contact to connect to a base layer, wherein said base contact is deposited (i) on top of said InGaP emitter layer and then alloyed to said base layer by annealing or (ii) on top of said base layer after etching off said InGaP emitter layer; (D) forming a base-collector mesa by etching off said base layer and partially or entirely etching off a collector layer; (E) depositing a collector contact on a sub-collector layer; (F) forming a sub-collector isolation by one of (i) ion implantation or (ii) a mesa etch; (G) depositing a first passivation layer, wherein said first passivation layer (i) covers said emitter contact, said base contact and said collector contact and (ii) comprises an inorganic insulator; (H) forming a silicon nitride opening on top of said emitter contact, said base contact and said collector contact by 23 dry etching; 24 (I) depositing a second passivation layer on top of said first passivation layer, wherein said second passivation layer comprises an inorganic insulator or organic polymer with low dielectric constant; (J) creating openings for electrical connections in said second passivation layer on top of said emitter contact, said base contact and collector contact; and (K) depositing an interconnect metal coupled to said emitter contact and separated second passivation layer, wherein said interconnect transistor.
The method according to claim 19, further nitride for a metal-insulator-metal capacitor and passivation layer and open via; (N) depositing a passivation layer comprises silicon nitride and said passivation layer and making openings on bond from said first passivation layer by said metal enables a connection to outside said comprising the steps of: (L) depositing silicon open silicon nitride via; (M) applying a third second interconnect metal, wherein said third organic polymer; and (0) forming a fourth pads.
Layer stacks claimed or described, ordered top of device to substrate.
InGaP/GaAs Heterojunction Bipolar Transistor (HBT)
High Electron Mobility Transistor (HEMT)/pseudomorphic HEMT (pHEMT)
No layer stack recorded.
Materials described outside the worked examples.
GaAs substrate
GaAs
inorganic insulator (first passivation layer)
organic polymer with low dielectric constant (second passivation layer)
InGaAs base layer
InGaAs
GaAsSb base layer
GaAsSb
GaInAsN base layer
GaInAsN
InGaP emitter layer
InGaP
AlGaAs emitter layer
AlGaAs
silicon nitride (first passivation layer)
Si₃N₄
Polyimide or BCB (second passivation layer)
polyimide low-k passivation layer
BCB low-k passivation layer
n+ InGaAs/GaAs emitter contact layer
InGaAs/GaAs
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 1 nm | — |
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The device 100 a may further comprise multiple emitter contact layers 124a-124b and corresponding emitter contact metals 130a-130b and either one base …
FIG. 2, a diagram illustrating an example emb diment of the present invention having multi-emitters is shown. A cross-sectional view of the device 100 a is …
FIG. 3. The device 100 c may not implement the collector layer region 108b next to the collector contact metal 126. The passivation layer 110 and the low-k …
FIG. 4. The contact site 220a may be a relatively flat region between the collector layer 108 (e.g., the slope of the base-collector mesa 140) and the collector …
FIG. 5, a diagram illustrating a base-collector mesa etch through a collector layer is shown. A cross-sectional view of the device 100 d is shown. The device …
FIG. 6, a diagram illustrating a base feedline and a base-collector mesa having a positive slope is shown. A cross-sectional view 300a is shown. The …
FIG. 7, a diagram illustrating a base feedline and base-collector mesa having a negative slope is shown. A cross-sectional view 300b is shown. The …
FIG. 8, a diagram illustrating a feedline to an emitter contact is shown. A cross-sectional view 320 is shown. The cross-sectional view 320 may comprise a …
FIG. 9, a diagram illustrating a base contact metal on top of a GaAs base layer by opening an InGaP emitter layer is shown. A view 350a of a portion of an …
FIG. 10, a diagram illustrating a base contact metal on top of an InGaP emitter layer with an alloy through to enable metal to reach a GaAs base layer is …
FIG. 11, a diagram illustrating an interconnect metal to connect an emitter contact metal using a single emitter with an emitter feedline crossing over a …
FIG. 12, a diagram illustrating an interconnect metal with a copper pillar to connect an emitter contact metal using a multi-emitter is shown. A …
FIG. 13, a diagram illustrating an interconnect metal to connect an emitter contact metal using a multi-emitter is shown. A cross- sectional view of the device …
FIG. 14, a diagram illustrating an interconnect metal to connect a merged emitter contact metal using a multi-emitter is shown. A cross-sectional view of the …
FIG. 15, a diagram illustrating an HBT implemented as part of a BiHEMT structure is shown. A cross-sectional view of a structure 480 is shown. The structure …
FIG. 16, a diagram illustrating active layers of an HBT isolated from a base post is shown. A cross-sectional view of the device 100i is shown. The device 100i …
FIG. 17, a method (or process) 580 is shown. The method 580 may illustrate a fabrication of a low-parasitic, high-frequency InGaP/GaAs HBT. The method 580 may …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: a semiconductor die including a plurality of semiconductor layers disposed on a GaAs substrate; a first contact electrically coupled to a semiconductor emitter layer; a second contact electrically coupled to a semiconductor base layer; a third contact electrically coupled to a semiconductor sub-collector layer; a first passivation layer covering one or more of said semiconductor, said first contact, said second contact and said third contact, said first passivation layer comprises an inorganic insulator; a second passivation layer comprising an inorganic insulator or organic polymer with low dielectric constant deposited on said first passivation layer; and an interconnect metal coupled to said first contact and separated from said first passivation layer by said second passivation layer.
The device according to claim 1, further comprising: 2 an emitter mesa to make an island of emitter layers; 3 a base-collector mesa to make an island of base-collector layers; and a subcollector isolation to isolate said semiconductor sub-collector layer, wherein (a) said semiconductor sub-collector layer has a first band-gap, (b) said semiconductor emitter layer has a second band-gap and (c) said semiconductor base layer has a third band-gap.
The device according to claim 1, wherein (i) the device comprises of an integrated HBT and a field effect transistor (FET), (ii) epitaxial layers of the FET are under layers of the HBT and (iii) the FET comprises of a gate, a source, and a drain.
The device according to claim 1, wherein (i) the device comprises of an integrated HBT and a field effect transistor (FET), (ii) epitaxial layers of the FET are on top of layers of the 4 HBT and (iii) the FET comprises of a gate, a source, and a drain.
1 17. The device according to claim 1, wherein said first contact is separated from said second passivation layer by a third passivation layer comprising said inorganic insulator and a fourth passivation layer comprising said organic polymer with said low dielectric constant.
A device comprising: a semiconductor die including a plurality of semiconductor layers disposed on a GaAs substrate; a first contact electrically coupled to a semiconductor emitter layer; a second contact electrically coupled to a semiconductor base layer; a third contact electrically coupled to a semiconductor sub-collector layer; a first passivation layer covering one or more of said semiconductor, said first contact, said second contact and said third contact, said first passivation layer comprises an inorganic insulator; an interconnect metal coupled to said first contact; and an air-gap formed between said first passivation layer and said interconnect metal, wherein said air-gap is formed by (i) depositing a sacrificial material on said first passivation layer 18 and (ii) removing said sacrificial material to leave said air-gap.
1 19. A method for fabricating a transistor comprising the steps of: (A) depositing an emitter contact; (B) forming an emitter mesa by (i) etching off emitter cap layers and (ii) stopping at an InGaP emitter layer; (C) depositing a base contact to connect to a base layer, wherein said base contact is deposited (i) on top of said InGaP emitter layer and then alloyed to said base layer by annealing or (ii) on top of said base layer after etching off said InGaP emitter layer; (D) forming a base-collector mesa by etching off said base layer and partially or entirely etching off a collector layer; (E) depositing a collector contact on a sub-collector layer; (F) forming a sub-collector isolation by one of (i) ion implantation or (ii) a mesa etch; (G) depositing a first passivation layer, wherein said first passivation layer (i) covers said emitter contact, said base contact and said collector contact and (ii) comprises an inorganic insulator; (H) forming a silicon nitride opening on top of said emitter contact, said base contact and said collector contact by 23 dry etching; 24 (I) depositing a second passivation layer on top of said first passivation layer, wherein said second passivation layer comprises an inorganic insulator or organic polymer with low dielectric constant; (J) creating openings for electrical connections in said second passivation layer on top of said emitter contact, said base contact and collector contact; and (K) depositing an interconnect metal coupled to said emitter contact and separated second passivation layer, wherein said interconnect transistor.
The method according to claim 19, further nitride for a metal-insulator-metal capacitor and passivation layer and open via; (N) depositing a passivation layer comprises silicon nitride and said passivation layer and making openings on bond from said first passivation layer by said metal enables a connection to outside said comprising the steps of: (L) depositing silicon open silicon nitride via; (M) applying a third second interconnect metal, wherein said third organic polymer; and (0) forming a fourth pads.
Layer stacks claimed or described, ordered top of device to substrate.
InGaP/GaAs Heterojunction Bipolar Transistor (HBT)
High Electron Mobility Transistor (HEMT)/pseudomorphic HEMT (pHEMT)
No layer stack recorded.
Materials described outside the worked examples.
GaAs substrate
GaAs
inorganic insulator (first passivation layer)
organic polymer with low dielectric constant (second passivation layer)
InGaAs base layer
InGaAs
GaAsSb base layer
GaAsSb
GaInAsN base layer
GaInAsN
InGaP emitter layer
InGaP
AlGaAs emitter layer
AlGaAs
silicon nitride (first passivation layer)
Si₃N₄
Polyimide or BCB (second passivation layer)
polyimide low-k passivation layer
BCB low-k passivation layer
n+ InGaAs/GaAs emitter contact layer
InGaAs/GaAs
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 1 nm | — |
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The device 100 a may further comprise multiple emitter contact layers 124a-124b and corresponding emitter contact metals 130a-130b and either one base …
FIG. 2, a diagram illustrating an example emb diment of the present invention having multi-emitters is shown. A cross-sectional view of the device 100 a is …
FIG. 3. The device 100 c may not implement the collector layer region 108b next to the collector contact metal 126. The passivation layer 110 and the low-k …
FIG. 4. The contact site 220a may be a relatively flat region between the collector layer 108 (e.g., the slope of the base-collector mesa 140) and the collector …
FIG. 5, a diagram illustrating a base-collector mesa etch through a collector layer is shown. A cross-sectional view of the device 100 d is shown. The device …
FIG. 6, a diagram illustrating a base feedline and a base-collector mesa having a positive slope is shown. A cross-sectional view 300a is shown. The …
FIG. 7, a diagram illustrating a base feedline and base-collector mesa having a negative slope is shown. A cross-sectional view 300b is shown. The …
FIG. 8, a diagram illustrating a feedline to an emitter contact is shown. A cross-sectional view 320 is shown. The cross-sectional view 320 may comprise a …
FIG. 9, a diagram illustrating a base contact metal on top of a GaAs base layer by opening an InGaP emitter layer is shown. A view 350a of a portion of an …
FIG. 10, a diagram illustrating a base contact metal on top of an InGaP emitter layer with an alloy through to enable metal to reach a GaAs base layer is …
FIG. 11, a diagram illustrating an interconnect metal to connect an emitter contact metal using a single emitter with an emitter feedline crossing over a …
FIG. 12, a diagram illustrating an interconnect metal with a copper pillar to connect an emitter contact metal using a multi-emitter is shown. A …
FIG. 13, a diagram illustrating an interconnect metal to connect an emitter contact metal using a multi-emitter is shown. A cross- sectional view of the device …
FIG. 14, a diagram illustrating an interconnect metal to connect a merged emitter contact metal using a multi-emitter is shown. A cross-sectional view of the …
FIG. 15, a diagram illustrating an HBT implemented as part of a BiHEMT structure is shown. A cross-sectional view of a structure 480 is shown. The structure …
FIG. 16, a diagram illustrating active layers of an HBT isolated from a base post is shown. A cross-sectional view of the device 100i is shown. The device 100i …
FIG. 17, a method (or process) 580 is shown. The method 580 may illustrate a fabrication of a low-parasitic, high-frequency InGaP/GaAs HBT. The method 580 may …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: a semiconductor die including a plurality of semiconductor layers disposed on a GaAs substrate; a first contact electrically coupled to a semiconductor emitter layer; a second contact electrically coupled to a semiconductor base layer; a third contact electrically coupled to a semiconductor sub-collector layer; a first passivation layer covering one or more of said semiconductor, said first contact, said second contact and said third contact, said first passivation layer comprises an inorganic insulator; a second passivation layer comprising an inorganic insulator or organic polymer with low dielectric constant deposited on said first passivation layer; and an interconnect metal coupled to said first contact and separated from said first passivation layer by said second passivation layer.
The device according to claim 1, further comprising: 2 an emitter mesa to make an island of emitter layers; 3 a base-collector mesa to make an island of base-collector layers; and a subcollector isolation to isolate said semiconductor sub-collector layer, wherein (a) said semiconductor sub-collector layer has a first band-gap, (b) said semiconductor emitter layer has a second band-gap and (c) said semiconductor base layer has a third band-gap.
The device according to claim 1, wherein (i) the device comprises of an integrated HBT and a field effect transistor (FET), (ii) epitaxial layers of the FET are under layers of the HBT and (iii) the FET comprises of a gate, a source, and a drain.
The device according to claim 1, wherein (i) the device comprises of an integrated HBT and a field effect transistor (FET), (ii) epitaxial layers of the FET are on top of layers of the 4 HBT and (iii) the FET comprises of a gate, a source, and a drain.
1 17. The device according to claim 1, wherein said first contact is separated from said second passivation layer by a third passivation layer comprising said inorganic insulator and a fourth passivation layer comprising said organic polymer with said low dielectric constant.
A device comprising: a semiconductor die including a plurality of semiconductor layers disposed on a GaAs substrate; a first contact electrically coupled to a semiconductor emitter layer; a second contact electrically coupled to a semiconductor base layer; a third contact electrically coupled to a semiconductor sub-collector layer; a first passivation layer covering one or more of said semiconductor, said first contact, said second contact and said third contact, said first passivation layer comprises an inorganic insulator; an interconnect metal coupled to said first contact; and an air-gap formed between said first passivation layer and said interconnect metal, wherein said air-gap is formed by (i) depositing a sacrificial material on said first passivation layer 18 and (ii) removing said sacrificial material to leave said air-gap.
1 19. A method for fabricating a transistor comprising the steps of: (A) depositing an emitter contact; (B) forming an emitter mesa by (i) etching off emitter cap layers and (ii) stopping at an InGaP emitter layer; (C) depositing a base contact to connect to a base layer, wherein said base contact is deposited (i) on top of said InGaP emitter layer and then alloyed to said base layer by annealing or (ii) on top of said base layer after etching off said InGaP emitter layer; (D) forming a base-collector mesa by etching off said base layer and partially or entirely etching off a collector layer; (E) depositing a collector contact on a sub-collector layer; (F) forming a sub-collector isolation by one of (i) ion implantation or (ii) a mesa etch; (G) depositing a first passivation layer, wherein said first passivation layer (i) covers said emitter contact, said base contact and said collector contact and (ii) comprises an inorganic insulator; (H) forming a silicon nitride opening on top of said emitter contact, said base contact and said collector contact by 23 dry etching; 24 (I) depositing a second passivation layer on top of said first passivation layer, wherein said second passivation layer comprises an inorganic insulator or organic polymer with low dielectric constant; (J) creating openings for electrical connections in said second passivation layer on top of said emitter contact, said base contact and collector contact; and (K) depositing an interconnect metal coupled to said emitter contact and separated second passivation layer, wherein said interconnect transistor.
The method according to claim 19, further nitride for a metal-insulator-metal capacitor and passivation layer and open via; (N) depositing a passivation layer comprises silicon nitride and said passivation layer and making openings on bond from said first passivation layer by said metal enables a connection to outside said comprising the steps of: (L) depositing silicon open silicon nitride via; (M) applying a third second interconnect metal, wherein said third organic polymer; and (0) forming a fourth pads.
Layer stacks claimed or described, ordered top of device to substrate.
InGaP/GaAs Heterojunction Bipolar Transistor (HBT)
High Electron Mobility Transistor (HEMT)/pseudomorphic HEMT (pHEMT)
No layer stack recorded.
Materials described outside the worked examples.
GaAs substrate
GaAs
inorganic insulator (first passivation layer)
organic polymer with low dielectric constant (second passivation layer)
InGaAs base layer
InGaAs
GaAsSb base layer
GaAsSb
GaInAsN base layer
GaInAsN
InGaP emitter layer
InGaP
AlGaAs emitter layer
AlGaAs
silicon nitride (first passivation layer)
Si₃N₄
Polyimide or BCB (second passivation layer)
polyimide low-k passivation layer
BCB low-k passivation layer
n+ InGaAs/GaAs emitter contact layer
InGaAs/GaAs
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 1 nm | — |
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