Patent
Atlas literature
Patent
US 12,261,519 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an integrated GaN power device, and a silicon device, in the same package, according to an embodi- ment of the disclosure;
FIG. 2 illustrates schematic of a gate driver circuit with energy harvesting, integrated pull-up and pull-down transis- 10 tors, and voltage clamping features …
FIG. 3 shows a graph of a quiescent current at an input terminal of the gate driver circuit shown in
FIG. 4A illustrates schematic of a circuit with saturation current protection feature according to an embodiment of the disclosure;
FIG. 5 illustrates schematic of a circuit with saturation current protection feature according to an embodiment of the disclosure;
FIG. 6 illustrates schematic of a circuit with saturation 25 current protection feature according to an embodiment of the disclosure;
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
FIG. 8 illustrates schematic of a gate driver and control circuit with turn-on dv/dt control and gate clamping fea- tures, according to an embodiment of the …
FIG. 9 illustrates schematic of a circuit with turn-off dI/dt 40 control feature according to an embodiment of the disclo- sure;
FIG. 10 illustrates schematic of a gate driver circuit with hysteresis according to an embodiment of the disclosure;
FIG. 11 illustrates voltages at various nodes within the 45 gate circuit of
FIG. 12 illustrates schematic of a voltage regulator in accordance with an embodiment of the disclosure;
FIG. 13 illustrates an integrated GaN power device in a TO-247 package according to an embodiment of the disclo- 50 sure; and
FIG. 14B illustrates an integrated GaN power device in a four-terminal TO-247 package according to an embodiment of the disclo- 55 sure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A circuit comprising: a first transistor including a first drain terminal, a first gate terminal and a first source terminal; a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal; and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation.
The circuit of claim 1, wherein the first transistor comprises gallium nitride (GaN).
The circuit of claim 1, wherein the depletion-mode transistor comprises GaN.
The circuit of claim 1, further comprising a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.
The circuit of claim 1, further comprising a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first and second gate terminals.
The circuit of claim 1, wherein the comparator is further arranged to transition the first transistor from an off-state to an on-state in response to the first transistor exiting its saturation region of operation.
The circuit of claim 1, wherein the second gate terminal is coupled to a ground node.
The circuit of claim 1, wherein the second source terminal is coupled to a resistor divider circuit.
A method of operating a circuit, the method compris-ing: providing a first transistor including a first drain terminal, a first gate terminal and a first source terminal; sensing, by a depletion-mode transistor, a voltage at the first drain terminal, wherein the depletion-mode tran-sistor includes a second drain terminal, a second gate terminal and a second source terminal, and wherein the second drain terminal is connected to the first drain terminal; 23 24 generating, by the depletion-mode transistor, a second voltage at the second source terminal; and receiving, by a comparator, the second voltage; and transitioning, by the comparator, the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation.
The method of claim 11, wherein the first transistor comprises gallium nitride (GaN).
The method of claim 11, wherein the depletion-mode transistor comprises GaN.
The method of claim 11, further comprising receiving, by a logic circuit, an output voltage generated by the comparator and driving, by the logic circuit, the first gate terminal.
The method of claim 11, further comprising receiving, by a logic circuit, an output voltage generated by the comparator and driving, by the logic circuit, the first and second gate terminal.
The method of claim 11, wherein the comparator is arranged to transition the first transistor from an off-state to an on-state in response to the first transistor exiting its saturation region of operation.
The method of claim 11, wherein the second gate terminal is coupled to a ground node.
The method of claim 11, wherein the second source terminal is coupled to a resistor divider circuit.
Layer stacks claimed or described, ordered top of device to substrate.
integrated GaN power circuit with saturation protection
integrated GaN power device package
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates schematic of a gate driver circuit with energy harvesting, integrated pull-up and pull-down transis- 10 tors, and voltage clamping features …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0–15 V | — |
Voltage |
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Patent
Atlas literature
Patent
US 12,261,519 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an integrated GaN power device, and a silicon device, in the same package, according to an embodi- ment of the disclosure;
FIG. 2 illustrates schematic of a gate driver circuit with energy harvesting, integrated pull-up and pull-down transis- 10 tors, and voltage clamping features …
FIG. 3 shows a graph of a quiescent current at an input terminal of the gate driver circuit shown in
FIG. 4A illustrates schematic of a circuit with saturation current protection feature according to an embodiment of the disclosure;
FIG. 5 illustrates schematic of a circuit with saturation current protection feature according to an embodiment of the disclosure;
FIG. 6 illustrates schematic of a circuit with saturation 25 current protection feature according to an embodiment of the disclosure;
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
FIG. 8 illustrates schematic of a gate driver and control circuit with turn-on dv/dt control and gate clamping fea- tures, according to an embodiment of the …
FIG. 9 illustrates schematic of a circuit with turn-off dI/dt 40 control feature according to an embodiment of the disclo- sure;
FIG. 10 illustrates schematic of a gate driver circuit with hysteresis according to an embodiment of the disclosure;
FIG. 11 illustrates voltages at various nodes within the 45 gate circuit of
FIG. 12 illustrates schematic of a voltage regulator in accordance with an embodiment of the disclosure;
FIG. 13 illustrates an integrated GaN power device in a TO-247 package according to an embodiment of the disclo- 50 sure; and
FIG. 14B illustrates an integrated GaN power device in a four-terminal TO-247 package according to an embodiment of the disclo- 55 sure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A circuit comprising: a first transistor including a first drain terminal, a first gate terminal and a first source terminal; a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal; and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation.
The circuit of claim 1, wherein the first transistor comprises gallium nitride (GaN).
The circuit of claim 1, wherein the depletion-mode transistor comprises GaN.
The circuit of claim 1, further comprising a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.
The circuit of claim 1, further comprising a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first and second gate terminals.
The circuit of claim 1, wherein the comparator is further arranged to transition the first transistor from an off-state to an on-state in response to the first transistor exiting its saturation region of operation.
The circuit of claim 1, wherein the second gate terminal is coupled to a ground node.
The circuit of claim 1, wherein the second source terminal is coupled to a resistor divider circuit.
A method of operating a circuit, the method compris-ing: providing a first transistor including a first drain terminal, a first gate terminal and a first source terminal; sensing, by a depletion-mode transistor, a voltage at the first drain terminal, wherein the depletion-mode tran-sistor includes a second drain terminal, a second gate terminal and a second source terminal, and wherein the second drain terminal is connected to the first drain terminal; 23 24 generating, by the depletion-mode transistor, a second voltage at the second source terminal; and receiving, by a comparator, the second voltage; and transitioning, by the comparator, the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation.
The method of claim 11, wherein the first transistor comprises gallium nitride (GaN).
The method of claim 11, wherein the depletion-mode transistor comprises GaN.
The method of claim 11, further comprising receiving, by a logic circuit, an output voltage generated by the comparator and driving, by the logic circuit, the first gate terminal.
The method of claim 11, further comprising receiving, by a logic circuit, an output voltage generated by the comparator and driving, by the logic circuit, the first and second gate terminal.
The method of claim 11, wherein the comparator is arranged to transition the first transistor from an off-state to an on-state in response to the first transistor exiting its saturation region of operation.
The method of claim 11, wherein the second gate terminal is coupled to a ground node.
The method of claim 11, wherein the second source terminal is coupled to a resistor divider circuit.
Layer stacks claimed or described, ordered top of device to substrate.
integrated GaN power circuit with saturation protection
integrated GaN power device package
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates schematic of a gate driver circuit with energy harvesting, integrated pull-up and pull-down transis- 10 tors, and voltage clamping features …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0–15 V | — |
Voltage |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 20
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,261,519 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an integrated GaN power device, and a silicon device, in the same package, according to an embodi- ment of the disclosure;
FIG. 2 illustrates schematic of a gate driver circuit with energy harvesting, integrated pull-up and pull-down transis- 10 tors, and voltage clamping features …
FIG. 3 shows a graph of a quiescent current at an input terminal of the gate driver circuit shown in
FIG. 4A illustrates schematic of a circuit with saturation current protection feature according to an embodiment of the disclosure;
FIG. 5 illustrates schematic of a circuit with saturation current protection feature according to an embodiment of the disclosure;
FIG. 6 illustrates schematic of a circuit with saturation 25 current protection feature according to an embodiment of the disclosure;
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
FIG. 8 illustrates schematic of a gate driver and control circuit with turn-on dv/dt control and gate clamping fea- tures, according to an embodiment of the …
FIG. 9 illustrates schematic of a circuit with turn-off dI/dt 40 control feature according to an embodiment of the disclo- sure;
FIG. 10 illustrates schematic of a gate driver circuit with hysteresis according to an embodiment of the disclosure;
FIG. 11 illustrates voltages at various nodes within the 45 gate circuit of
FIG. 12 illustrates schematic of a voltage regulator in accordance with an embodiment of the disclosure;
FIG. 13 illustrates an integrated GaN power device in a TO-247 package according to an embodiment of the disclo- 50 sure; and
FIG. 14B illustrates an integrated GaN power device in a four-terminal TO-247 package according to an embodiment of the disclo- 55 sure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A circuit comprising: a first transistor including a first drain terminal, a first gate terminal and a first source terminal; a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal; and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation.
The circuit of claim 1, wherein the first transistor comprises gallium nitride (GaN).
The circuit of claim 1, wherein the depletion-mode transistor comprises GaN.
The circuit of claim 1, further comprising a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.
The circuit of claim 1, further comprising a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first and second gate terminals.
The circuit of claim 1, wherein the comparator is further arranged to transition the first transistor from an off-state to an on-state in response to the first transistor exiting its saturation region of operation.
The circuit of claim 1, wherein the second gate terminal is coupled to a ground node.
The circuit of claim 1, wherein the second source terminal is coupled to a resistor divider circuit.
A method of operating a circuit, the method compris-ing: providing a first transistor including a first drain terminal, a first gate terminal and a first source terminal; sensing, by a depletion-mode transistor, a voltage at the first drain terminal, wherein the depletion-mode tran-sistor includes a second drain terminal, a second gate terminal and a second source terminal, and wherein the second drain terminal is connected to the first drain terminal; 23 24 generating, by the depletion-mode transistor, a second voltage at the second source terminal; and receiving, by a comparator, the second voltage; and transitioning, by the comparator, the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation.
The method of claim 11, wherein the first transistor comprises gallium nitride (GaN).
The method of claim 11, wherein the depletion-mode transistor comprises GaN.
The method of claim 11, further comprising receiving, by a logic circuit, an output voltage generated by the comparator and driving, by the logic circuit, the first gate terminal.
The method of claim 11, further comprising receiving, by a logic circuit, an output voltage generated by the comparator and driving, by the logic circuit, the first and second gate terminal.
The method of claim 11, wherein the comparator is arranged to transition the first transistor from an off-state to an on-state in response to the first transistor exiting its saturation region of operation.
The method of claim 11, wherein the second gate terminal is coupled to a ground node.
The method of claim 11, wherein the second source terminal is coupled to a resistor divider circuit.
Layer stacks claimed or described, ordered top of device to substrate.
integrated GaN power circuit with saturation protection
integrated GaN power device package
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates schematic of a gate driver circuit with energy harvesting, integrated pull-up and pull-down transis- 10 tors, and voltage clamping features …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0–15 V | — |
Voltage |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 20
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,261,519 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an integrated GaN power device, and a silicon device, in the same package, according to an embodi- ment of the disclosure;
FIG. 2 illustrates schematic of a gate driver circuit with energy harvesting, integrated pull-up and pull-down transis- 10 tors, and voltage clamping features …
FIG. 3 shows a graph of a quiescent current at an input terminal of the gate driver circuit shown in
FIG. 4A illustrates schematic of a circuit with saturation current protection feature according to an embodiment of the disclosure;
FIG. 5 illustrates schematic of a circuit with saturation current protection feature according to an embodiment of the disclosure;
FIG. 6 illustrates schematic of a circuit with saturation 25 current protection feature according to an embodiment of the disclosure;
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
FIG. 8 illustrates schematic of a gate driver and control circuit with turn-on dv/dt control and gate clamping fea- tures, according to an embodiment of the …
FIG. 9 illustrates schematic of a circuit with turn-off dI/dt 40 control feature according to an embodiment of the disclo- sure;
FIG. 10 illustrates schematic of a gate driver circuit with hysteresis according to an embodiment of the disclosure;
FIG. 11 illustrates voltages at various nodes within the 45 gate circuit of
FIG. 12 illustrates schematic of a voltage regulator in accordance with an embodiment of the disclosure;
FIG. 13 illustrates an integrated GaN power device in a TO-247 package according to an embodiment of the disclo- 50 sure; and
FIG. 14B illustrates an integrated GaN power device in a four-terminal TO-247 package according to an embodiment of the disclo- 55 sure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A circuit comprising: a first transistor including a first drain terminal, a first gate terminal and a first source terminal; a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal; and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation.
The circuit of claim 1, wherein the first transistor comprises gallium nitride (GaN).
The circuit of claim 1, wherein the depletion-mode transistor comprises GaN.
The circuit of claim 1, further comprising a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.
The circuit of claim 1, further comprising a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first and second gate terminals.
The circuit of claim 1, wherein the comparator is further arranged to transition the first transistor from an off-state to an on-state in response to the first transistor exiting its saturation region of operation.
The circuit of claim 1, wherein the second gate terminal is coupled to a ground node.
The circuit of claim 1, wherein the second source terminal is coupled to a resistor divider circuit.
A method of operating a circuit, the method compris-ing: providing a first transistor including a first drain terminal, a first gate terminal and a first source terminal; sensing, by a depletion-mode transistor, a voltage at the first drain terminal, wherein the depletion-mode tran-sistor includes a second drain terminal, a second gate terminal and a second source terminal, and wherein the second drain terminal is connected to the first drain terminal; 23 24 generating, by the depletion-mode transistor, a second voltage at the second source terminal; and receiving, by a comparator, the second voltage; and transitioning, by the comparator, the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation.
The method of claim 11, wherein the first transistor comprises gallium nitride (GaN).
The method of claim 11, wherein the depletion-mode transistor comprises GaN.
The method of claim 11, further comprising receiving, by a logic circuit, an output voltage generated by the comparator and driving, by the logic circuit, the first gate terminal.
The method of claim 11, further comprising receiving, by a logic circuit, an output voltage generated by the comparator and driving, by the logic circuit, the first and second gate terminal.
The method of claim 11, wherein the comparator is arranged to transition the first transistor from an off-state to an on-state in response to the first transistor exiting its saturation region of operation.
The method of claim 11, wherein the second gate terminal is coupled to a ground node.
The method of claim 11, wherein the second source terminal is coupled to a resistor divider circuit.
Layer stacks claimed or described, ordered top of device to substrate.
integrated GaN power circuit with saturation protection
integrated GaN power device package
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates schematic of a gate driver circuit with energy harvesting, integrated pull-up and pull-down transis- 10 tors, and voltage clamping features …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0–15 V | — |
Voltage |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 20
Related documents with shared materials, methods, properties, or citations.
FIG. 2 illustrates schematic of a gate driver circuit with energy harvesting, integrated pull-up and pull-down transis- 10 tors, and voltage clamping features …
FIG. 3 shows a graph of a quiescent current at an input terminal of the gate driver circuit shown in
FIG. 4A illustrates schematic of a circuit with saturation current protection feature according to an embodiment of the disclosure;
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
| — |
Voltage | 10–30 V | — |
Voltage | 0–6 V | — |
Voltage | 0–400 V | — |
Voltage | 10–20 V | — |
Voltage | 1–50 V | — |
Voltage | ≤ 6 V | — |
Voltage | ≤ 5.9 V | — |
Cited non-patent literature · 3
FIG. 2 illustrates schematic of a gate driver circuit with energy harvesting, integrated pull-up and pull-down transis- 10 tors, and voltage clamping features …
FIG. 3 shows a graph of a quiescent current at an input terminal of the gate driver circuit shown in
FIG. 4A illustrates schematic of a circuit with saturation current protection feature according to an embodiment of the disclosure;
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
| — |
Voltage | 10–30 V | — |
Voltage | 0–6 V | — |
Voltage | 0–400 V | — |
Voltage | 10–20 V | — |
Voltage | 1–50 V | — |
Voltage | ≤ 6 V | — |
Voltage | ≤ 5.9 V | — |
Cited non-patent literature · 3
FIG. 2 illustrates schematic of a gate driver circuit with energy harvesting, integrated pull-up and pull-down transis- 10 tors, and voltage clamping features …
FIG. 3 shows a graph of a quiescent current at an input terminal of the gate driver circuit shown in
FIG. 4A illustrates schematic of a circuit with saturation current protection feature according to an embodiment of the disclosure;
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
| — |
Voltage | 10–30 V | — |
Voltage | 0–6 V | — |
Voltage | 0–400 V | — |
Voltage | 10–20 V | — |
Voltage | 1–50 V | — |
Voltage | ≤ 6 V | — |
Voltage | ≤ 5.9 V | — |
Cited non-patent literature · 3
FIG. 2 illustrates schematic of a gate driver circuit with energy harvesting, integrated pull-up and pull-down transis- 10 tors, and voltage clamping features …
FIG. 3 shows a graph of a quiescent current at an input terminal of the gate driver circuit shown in
FIG. 4A illustrates schematic of a circuit with saturation current protection feature according to an embodiment of the disclosure;
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
FIG. 7C shows rate of change of drain-to-source voltage as a function of time as a function of resistance value of an 35 external resistor in the circuit of
| — |
Voltage | 10–30 V | — |
Voltage | 0–6 V | — |
Voltage | 0–400 V | — |
Voltage | 10–20 V | — |
Voltage | 1–50 V | — |
Voltage | ≤ 6 V | — |
Voltage | ≤ 5.9 V | — |
Cited non-patent literature · 3
