Patent
US 9,685,516ELECTRONIC DEVICE HAVING GRAPHENE-SEMICONDUCTOR MULTI-JUNCTION AND METHOD OF MANUFACTURING THE ELECTRONIC DEVICE
Hyeonjin SHIN
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 9,685,516Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating an electronic device having an increased graphene-semiconductor junction region, according to at least one …
FIG. 2 is a cross-sectional view illustrating a case where heights of protrusions of a graphene layer of
FIGS. 3 and 4 are cross-sectional views illustrating a method of manufacturing an electronic device, according to at least one example embodiment; [0026]
FIG. 4. The semiconductor layer 74A may be formed of the same material as the material of the semiconductor layer 50 of
FIG. 5 is a graph illustrating a Raman shift for a resultant structure obtained through low- temperature annealing in the example method illustrated at
FIG. 6 is a graph illustrating a Raman shift for a resultant structure obtained through high- temperature annealing in the example method illustrated at
FIGS. 7A through 11 are cross-sectional views for explaining a method of manufacturing an electronic device, according to another example embodiment.
FIGS. 8a and 8b, a semiconductor layer 88 is formed on the graphene layer 72. The semiconductor layer 88 may be formed by converting the oxide film 84 of
FIG. 10, the first substrate 70 is separated from the graphene layer 72. Alternatively, the graphene layer 72 and the semiconductor layer 88 are separated from …
FIG. 11, the graphene layer 72 and the semiconductor layer 88 are transferred to a second substrate 90. The second substrate 90 may be a flexible substrate. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising: a substrate; a graphene layer on the substrate; and a semiconductor layer covering the graphene layer, wherein the graphene layer includes a plurality of nanocrystal graphenes and a plurality of graphene protrusions, the graphene protrusions extending away from the graphene layer in an opposite direction to the substrate and including the nanocrystal graphenes in a stacking configuration and spaced apart from each other, wherein the graphene protrusions are connected to each other by the plurality of nanocrystal graphenes.
The electronic device of claim 1, wherein a side surface of one or more of the plurality of graphene protrusions is uneven.
The electronic device of claim 1, wherein one or more of the plurality of graphene protrusions comprises a plurality of nanocrystal graphenes.
The electronic device of claim 1, wherein heights of the plurality of graphene protrusions are different from each other.
The electronic device of claim 1, wherein the substrate is a flexible substrate.
The electronic device of claim 1, wherein the semiconductor layer comprises a transition metal dichalcogenide (TMDC) layer.
The electronic device of claim 1, wherein the graphene layer comprises: a lower graphene layer including the plurality of nanocrystal graphenes; and the plurality of graphene protrusions on the lower graphene layer.
The electronic device of claim 1, wherein the semiconductor layer is in direct contact with the graphene layer.
The electronic device of claim 1, wherein the graphene protrusions have a tapered configuration with lower layers being larger than upper layers.
The electronic device of claim 1, wherein the graphene protrusions have a pyramidal configuration.
The electronic device of claim 1, wherein the graphene protrusions have a substantially symmetrical configuration. *** END CLAIM LISTING *** Page 6
(Withdrawn-Currently Amended) A method of manufacturing an electronic device, the method comprising: forming on a first substrate a graphene layer that includes a plurality of nanocrystal graphenes; forming a semiconductor layer on the graphene layer; separating the first substrate from the graphene layer; and transferring the graphene layer and the semiconductor layer to a second substrate that is more flexible than the first substrate, wherein the graphene layer includes a plurality of graphene protrusions, the graphene protrusions extending away from the graphene layer in an opposite direction to the substrate and including the nanocrystal graphenes in a stacking configuration and spaced apart from each other, Page 3 Application No. 14/657,306 Attorney Docket No. 2557S I -00222 1 -US wherein the graphene protrusions are connected to each other by the plurality of the nanocrystal graphenes.
The method of claim 10, wherein the forming of the semiconductor layer comprises: coating a semiconductor solution layer in a s o l-gel state on the graphene layer; and annealing the graphene layer coated with the semiconductor solution layer. withdrawn
The method of claim 10, wherein the forming of the semiconductor layer comprises: forming on the graphene layer an oxide film that includes at least one portion of components of the semiconductor layer; converting the oxide film into a semiconductor material film having a same material as the semiconductor layer; and growing the semiconductor material film. withdrawn
The method of claim 10, wherein the semiconductor layer comprises a transition metal dichalcogenide (TMDC) layer. withdrawn
The method of claim 10, wherein the forming of the graphene layer comprises: forming on the first substrate a lower graphene layer including the plurality of nanocrystal graphenes; and forming the plurality of graphene protrusions on the lower graphene layer. withdrawn
The method of claim 10, wherein a side surface of one or more of the plurality of graphene protrusions is uneven. withdrawn
The method of claim 10, wherein the semiconductor layer is in Page 5 Application No. 14/657,306 Attorney Docket No. 2557SI-002221-US direct contact with the graphene layer. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
electronic device with graphene-semiconductor multi-junction
Materials described outside the worked examples.
nanocrystal graphene
graphene (lower graphene layer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a graph illustrating a Raman shift for a resultant structure obtained through low- temperature annealing in the example method illustrated at
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Flow Rate | 100–200 sccm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,685,516Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating an electronic device having an increased graphene-semiconductor junction region, according to at least one …
FIG. 2 is a cross-sectional view illustrating a case where heights of protrusions of a graphene layer of
FIGS. 3 and 4 are cross-sectional views illustrating a method of manufacturing an electronic device, according to at least one example embodiment; [0026]
FIG. 4. The semiconductor layer 74A may be formed of the same material as the material of the semiconductor layer 50 of
FIG. 5 is a graph illustrating a Raman shift for a resultant structure obtained through low- temperature annealing in the example method illustrated at
FIG. 6 is a graph illustrating a Raman shift for a resultant structure obtained through high- temperature annealing in the example method illustrated at
FIGS. 7A through 11 are cross-sectional views for explaining a method of manufacturing an electronic device, according to another example embodiment.
FIGS. 8a and 8b, a semiconductor layer 88 is formed on the graphene layer 72. The semiconductor layer 88 may be formed by converting the oxide film 84 of
FIG. 10, the first substrate 70 is separated from the graphene layer 72. Alternatively, the graphene layer 72 and the semiconductor layer 88 are separated from …
FIG. 11, the graphene layer 72 and the semiconductor layer 88 are transferred to a second substrate 90. The second substrate 90 may be a flexible substrate. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising: a substrate; a graphene layer on the substrate; and a semiconductor layer covering the graphene layer, wherein the graphene layer includes a plurality of nanocrystal graphenes and a plurality of graphene protrusions, the graphene protrusions extending away from the graphene layer in an opposite direction to the substrate and including the nanocrystal graphenes in a stacking configuration and spaced apart from each other, wherein the graphene protrusions are connected to each other by the plurality of nanocrystal graphenes.
The electronic device of claim 1, wherein a side surface of one or more of the plurality of graphene protrusions is uneven.
The electronic device of claim 1, wherein one or more of the plurality of graphene protrusions comprises a plurality of nanocrystal graphenes.
The electronic device of claim 1, wherein heights of the plurality of graphene protrusions are different from each other.
The electronic device of claim 1, wherein the substrate is a flexible substrate.
The electronic device of claim 1, wherein the semiconductor layer comprises a transition metal dichalcogenide (TMDC) layer.
The electronic device of claim 1, wherein the graphene layer comprises: a lower graphene layer including the plurality of nanocrystal graphenes; and the plurality of graphene protrusions on the lower graphene layer.
The electronic device of claim 1, wherein the semiconductor layer is in direct contact with the graphene layer.
The electronic device of claim 1, wherein the graphene protrusions have a tapered configuration with lower layers being larger than upper layers.
The electronic device of claim 1, wherein the graphene protrusions have a pyramidal configuration.
The electronic device of claim 1, wherein the graphene protrusions have a substantially symmetrical configuration. *** END CLAIM LISTING *** Page 6
(Withdrawn-Currently Amended) A method of manufacturing an electronic device, the method comprising: forming on a first substrate a graphene layer that includes a plurality of nanocrystal graphenes; forming a semiconductor layer on the graphene layer; separating the first substrate from the graphene layer; and transferring the graphene layer and the semiconductor layer to a second substrate that is more flexible than the first substrate, wherein the graphene layer includes a plurality of graphene protrusions, the graphene protrusions extending away from the graphene layer in an opposite direction to the substrate and including the nanocrystal graphenes in a stacking configuration and spaced apart from each other, Page 3 Application No. 14/657,306 Attorney Docket No. 2557S I -00222 1 -US wherein the graphene protrusions are connected to each other by the plurality of the nanocrystal graphenes.
The method of claim 10, wherein the forming of the semiconductor layer comprises: coating a semiconductor solution layer in a s o l-gel state on the graphene layer; and annealing the graphene layer coated with the semiconductor solution layer. withdrawn
The method of claim 10, wherein the forming of the semiconductor layer comprises: forming on the graphene layer an oxide film that includes at least one portion of components of the semiconductor layer; converting the oxide film into a semiconductor material film having a same material as the semiconductor layer; and growing the semiconductor material film. withdrawn
The method of claim 10, wherein the semiconductor layer comprises a transition metal dichalcogenide (TMDC) layer. withdrawn
The method of claim 10, wherein the forming of the graphene layer comprises: forming on the first substrate a lower graphene layer including the plurality of nanocrystal graphenes; and forming the plurality of graphene protrusions on the lower graphene layer. withdrawn
The method of claim 10, wherein a side surface of one or more of the plurality of graphene protrusions is uneven. withdrawn
The method of claim 10, wherein the semiconductor layer is in Page 5 Application No. 14/657,306 Attorney Docket No. 2557SI-002221-US direct contact with the graphene layer. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
electronic device with graphene-semiconductor multi-junction
Materials described outside the worked examples.
nanocrystal graphene
graphene (lower graphene layer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a graph illustrating a Raman shift for a resultant structure obtained through low- temperature annealing in the example method illustrated at
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Flow Rate | 100–200 sccm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,685,516Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating an electronic device having an increased graphene-semiconductor junction region, according to at least one …
FIG. 2 is a cross-sectional view illustrating a case where heights of protrusions of a graphene layer of
FIGS. 3 and 4 are cross-sectional views illustrating a method of manufacturing an electronic device, according to at least one example embodiment; [0026]
FIG. 4. The semiconductor layer 74A may be formed of the same material as the material of the semiconductor layer 50 of
FIG. 5 is a graph illustrating a Raman shift for a resultant structure obtained through low- temperature annealing in the example method illustrated at
FIG. 6 is a graph illustrating a Raman shift for a resultant structure obtained through high- temperature annealing in the example method illustrated at
FIGS. 7A through 11 are cross-sectional views for explaining a method of manufacturing an electronic device, according to another example embodiment.
FIGS. 8a and 8b, a semiconductor layer 88 is formed on the graphene layer 72. The semiconductor layer 88 may be formed by converting the oxide film 84 of
FIG. 10, the first substrate 70 is separated from the graphene layer 72. Alternatively, the graphene layer 72 and the semiconductor layer 88 are separated from …
FIG. 11, the graphene layer 72 and the semiconductor layer 88 are transferred to a second substrate 90. The second substrate 90 may be a flexible substrate. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising: a substrate; a graphene layer on the substrate; and a semiconductor layer covering the graphene layer, wherein the graphene layer includes a plurality of nanocrystal graphenes and a plurality of graphene protrusions, the graphene protrusions extending away from the graphene layer in an opposite direction to the substrate and including the nanocrystal graphenes in a stacking configuration and spaced apart from each other, wherein the graphene protrusions are connected to each other by the plurality of nanocrystal graphenes.
The electronic device of claim 1, wherein a side surface of one or more of the plurality of graphene protrusions is uneven.
The electronic device of claim 1, wherein one or more of the plurality of graphene protrusions comprises a plurality of nanocrystal graphenes.
The electronic device of claim 1, wherein heights of the plurality of graphene protrusions are different from each other.
The electronic device of claim 1, wherein the substrate is a flexible substrate.
The electronic device of claim 1, wherein the semiconductor layer comprises a transition metal dichalcogenide (TMDC) layer.
The electronic device of claim 1, wherein the graphene layer comprises: a lower graphene layer including the plurality of nanocrystal graphenes; and the plurality of graphene protrusions on the lower graphene layer.
The electronic device of claim 1, wherein the semiconductor layer is in direct contact with the graphene layer.
The electronic device of claim 1, wherein the graphene protrusions have a tapered configuration with lower layers being larger than upper layers.
The electronic device of claim 1, wherein the graphene protrusions have a pyramidal configuration.
The electronic device of claim 1, wherein the graphene protrusions have a substantially symmetrical configuration. *** END CLAIM LISTING *** Page 6
(Withdrawn-Currently Amended) A method of manufacturing an electronic device, the method comprising: forming on a first substrate a graphene layer that includes a plurality of nanocrystal graphenes; forming a semiconductor layer on the graphene layer; separating the first substrate from the graphene layer; and transferring the graphene layer and the semiconductor layer to a second substrate that is more flexible than the first substrate, wherein the graphene layer includes a plurality of graphene protrusions, the graphene protrusions extending away from the graphene layer in an opposite direction to the substrate and including the nanocrystal graphenes in a stacking configuration and spaced apart from each other, Page 3 Application No. 14/657,306 Attorney Docket No. 2557S I -00222 1 -US wherein the graphene protrusions are connected to each other by the plurality of the nanocrystal graphenes.
The method of claim 10, wherein the forming of the semiconductor layer comprises: coating a semiconductor solution layer in a s o l-gel state on the graphene layer; and annealing the graphene layer coated with the semiconductor solution layer. withdrawn
The method of claim 10, wherein the forming of the semiconductor layer comprises: forming on the graphene layer an oxide film that includes at least one portion of components of the semiconductor layer; converting the oxide film into a semiconductor material film having a same material as the semiconductor layer; and growing the semiconductor material film. withdrawn
The method of claim 10, wherein the semiconductor layer comprises a transition metal dichalcogenide (TMDC) layer. withdrawn
The method of claim 10, wherein the forming of the graphene layer comprises: forming on the first substrate a lower graphene layer including the plurality of nanocrystal graphenes; and forming the plurality of graphene protrusions on the lower graphene layer. withdrawn
The method of claim 10, wherein a side surface of one or more of the plurality of graphene protrusions is uneven. withdrawn
The method of claim 10, wherein the semiconductor layer is in Page 5 Application No. 14/657,306 Attorney Docket No. 2557SI-002221-US direct contact with the graphene layer. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
electronic device with graphene-semiconductor multi-junction
Materials described outside the worked examples.
nanocrystal graphene
graphene (lower graphene layer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a graph illustrating a Raman shift for a resultant structure obtained through low- temperature annealing in the example method illustrated at
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Flow Rate | 100–200 sccm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,685,516Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating an electronic device having an increased graphene-semiconductor junction region, according to at least one …
FIG. 2 is a cross-sectional view illustrating a case where heights of protrusions of a graphene layer of
FIGS. 3 and 4 are cross-sectional views illustrating a method of manufacturing an electronic device, according to at least one example embodiment; [0026]
FIG. 4. The semiconductor layer 74A may be formed of the same material as the material of the semiconductor layer 50 of
FIG. 5 is a graph illustrating a Raman shift for a resultant structure obtained through low- temperature annealing in the example method illustrated at
FIG. 6 is a graph illustrating a Raman shift for a resultant structure obtained through high- temperature annealing in the example method illustrated at
FIGS. 7A through 11 are cross-sectional views for explaining a method of manufacturing an electronic device, according to another example embodiment.
FIGS. 8a and 8b, a semiconductor layer 88 is formed on the graphene layer 72. The semiconductor layer 88 may be formed by converting the oxide film 84 of
FIG. 10, the first substrate 70 is separated from the graphene layer 72. Alternatively, the graphene layer 72 and the semiconductor layer 88 are separated from …
FIG. 11, the graphene layer 72 and the semiconductor layer 88 are transferred to a second substrate 90. The second substrate 90 may be a flexible substrate. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising: a substrate; a graphene layer on the substrate; and a semiconductor layer covering the graphene layer, wherein the graphene layer includes a plurality of nanocrystal graphenes and a plurality of graphene protrusions, the graphene protrusions extending away from the graphene layer in an opposite direction to the substrate and including the nanocrystal graphenes in a stacking configuration and spaced apart from each other, wherein the graphene protrusions are connected to each other by the plurality of nanocrystal graphenes.
The electronic device of claim 1, wherein a side surface of one or more of the plurality of graphene protrusions is uneven.
The electronic device of claim 1, wherein one or more of the plurality of graphene protrusions comprises a plurality of nanocrystal graphenes.
The electronic device of claim 1, wherein heights of the plurality of graphene protrusions are different from each other.
The electronic device of claim 1, wherein the substrate is a flexible substrate.
The electronic device of claim 1, wherein the semiconductor layer comprises a transition metal dichalcogenide (TMDC) layer.
The electronic device of claim 1, wherein the graphene layer comprises: a lower graphene layer including the plurality of nanocrystal graphenes; and the plurality of graphene protrusions on the lower graphene layer.
The electronic device of claim 1, wherein the semiconductor layer is in direct contact with the graphene layer.
The electronic device of claim 1, wherein the graphene protrusions have a tapered configuration with lower layers being larger than upper layers.
The electronic device of claim 1, wherein the graphene protrusions have a pyramidal configuration.
The electronic device of claim 1, wherein the graphene protrusions have a substantially symmetrical configuration. *** END CLAIM LISTING *** Page 6
(Withdrawn-Currently Amended) A method of manufacturing an electronic device, the method comprising: forming on a first substrate a graphene layer that includes a plurality of nanocrystal graphenes; forming a semiconductor layer on the graphene layer; separating the first substrate from the graphene layer; and transferring the graphene layer and the semiconductor layer to a second substrate that is more flexible than the first substrate, wherein the graphene layer includes a plurality of graphene protrusions, the graphene protrusions extending away from the graphene layer in an opposite direction to the substrate and including the nanocrystal graphenes in a stacking configuration and spaced apart from each other, Page 3 Application No. 14/657,306 Attorney Docket No. 2557S I -00222 1 -US wherein the graphene protrusions are connected to each other by the plurality of the nanocrystal graphenes.
The method of claim 10, wherein the forming of the semiconductor layer comprises: coating a semiconductor solution layer in a s o l-gel state on the graphene layer; and annealing the graphene layer coated with the semiconductor solution layer. withdrawn
The method of claim 10, wherein the forming of the semiconductor layer comprises: forming on the graphene layer an oxide film that includes at least one portion of components of the semiconductor layer; converting the oxide film into a semiconductor material film having a same material as the semiconductor layer; and growing the semiconductor material film. withdrawn
The method of claim 10, wherein the semiconductor layer comprises a transition metal dichalcogenide (TMDC) layer. withdrawn
The method of claim 10, wherein the forming of the graphene layer comprises: forming on the first substrate a lower graphene layer including the plurality of nanocrystal graphenes; and forming the plurality of graphene protrusions on the lower graphene layer. withdrawn
The method of claim 10, wherein a side surface of one or more of the plurality of graphene protrusions is uneven. withdrawn
The method of claim 10, wherein the semiconductor layer is in Page 5 Application No. 14/657,306 Attorney Docket No. 2557SI-002221-US direct contact with the graphene layer. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
electronic device with graphene-semiconductor multi-junction
Materials described outside the worked examples.
nanocrystal graphene
graphene (lower graphene layer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a graph illustrating a Raman shift for a resultant structure obtained through low- temperature annealing in the example method illustrated at
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Flow Rate | 100–200 sccm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
semiconductor layer/transition metal dichalcogenide (TMDC)
MoS₂ (molybdenite)
MoS₂
FIG. 5 is a graph illustrating a Raman shift for a resultant structure obtained through low- temperature annealing in the example method illustrated at
FIG. 6 is a graph illustrating a Raman shift for a resultant structure obtained through high- temperature annealing in the example method illustrated at
FIG. 6 is a graph illustrating a Raman shift for a resultant structure obtained through high- temperature annealing in the example method illustrated at
| 15–30 nm |
| — |
Flow Rate | 1–100 sccm | — |
semiconductor layer/transition metal dichalcogenide (TMDC)
MoS₂ (molybdenite)
MoS₂
FIG. 5 is a graph illustrating a Raman shift for a resultant structure obtained through low- temperature annealing in the example method illustrated at
FIG. 6 is a graph illustrating a Raman shift for a resultant structure obtained through high- temperature annealing in the example method illustrated at
FIG. 6 is a graph illustrating a Raman shift for a resultant structure obtained through high- temperature annealing in the example method illustrated at
| 15–30 nm |
| — |
Flow Rate | 1–100 sccm | — |
semiconductor layer/transition metal dichalcogenide (TMDC)
MoS₂ (molybdenite)
MoS₂
FIG. 5 is a graph illustrating a Raman shift for a resultant structure obtained through low- temperature annealing in the example method illustrated at
FIG. 6 is a graph illustrating a Raman shift for a resultant structure obtained through high- temperature annealing in the example method illustrated at
FIG. 6 is a graph illustrating a Raman shift for a resultant structure obtained through high- temperature annealing in the example method illustrated at
| 15–30 nm |
| — |
Flow Rate | 1–100 sccm | — |
semiconductor layer/transition metal dichalcogenide (TMDC)
MoS₂ (molybdenite)
MoS₂
FIG. 5 is a graph illustrating a Raman shift for a resultant structure obtained through low- temperature annealing in the example method illustrated at
FIG. 6 is a graph illustrating a Raman shift for a resultant structure obtained through high- temperature annealing in the example method illustrated at
FIG. 6 is a graph illustrating a Raman shift for a resultant structure obtained through high- temperature annealing in the example method illustrated at
| 15–30 nm |
| — |
Flow Rate | 1–100 sccm | — |