Patent
Atlas literature
Patent
US 12,592,640 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a block diagram of a system 100 including a half bridge circuit and the half bridge adjustment circuit, in accordance with one embodiment.
FIG. 2B. The portion 206 corresponds to the deadtime between times t7 and t8 preceding the rising edge of the second square wave signal 212. 25 In
FIG. 3B. The portion 306 corresponds to the deadtime between times t10 and t12 preceding the rising edge of the low side adjusted driver signal 312. In
FIG. 4A is a schematic diagram of a half bridge adjust- ment circuit, in accordance with one embodiment. 5
FIG. 5 is a cross-sectional view of an HEMT, in accor- dance with one embodiment. 10
FIG. 6 is a flow diagram of a method for operating a half bridge circuit, in accordance with one embodiment.
FIG. 7 is a flow diagram of a method for operating a half bridge circuit, in accordance with one embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: receiving, at a half bridge adjustment circuit, a first driver signal corresponding to a square wave; receiving, at the half bridge adjustment circuit, a second driver signal corresponding to a square wave, wherein a first deadtime is a period between a falling edge of the second driver signal and a rising edge of the first driver signal, wherein the first deadtime includes a first por-tion and a second portion following the first portion; generating, with the half bridge adjustment circuit, a first modified driver signal corresponding to the first driver signal with a transition from a low voltage to an intermediate voltage at a beginning of the second portion of the first deadtime and a transition from the intermediate voltage to a high voltage at an end of the first deadtime, wherein the first modified driver signal remains flat at the low voltage during the first portion of the first deadtime; and driving a gate terminal of a first transistor of a half bridge circuit with the first modified driver signal, wherein a second deadtime is a period between a falling edge of the first driver signal and a rising edge of the second driver signal; generating, with the half bridge adjustment circuit, a second modified driver signal corresponding to the second driver signal with a transition from the low voltage to the intermediate voltage during the second deadtime and a transition from the intermediate voltage to the high voltage at an end of the second deadtime; and driving a gate terminal of a second transistor of the half bridge circuit with the second modified driver signal.
The method of claim 1, generating the first and second driver signals with a driver, wherein the half bridge adjust-ment circuit and the driver are implemented in a same integrated circuit die to the half bridge circuit.
The method of claim 1, generating the first and second driver signals with a driver, wherein the driver is imple-mented in an integrated circuit, wherein the half bridge adjustment circuit is coupled between the integrated circuit and the half bridge circuit.
The method of claim 1, comprising generating, with the half bridge adjustment circuit, a deadtime signal having a high logic level during the first deadtime and during the second deadtime and having a low logic level outside the first deadtime and the second deadtime.
The method of claim 1, wherein the low voltage level is less than 0 V; and wherein the intermediate voltage is 0 V.
The method of claim 1, wherein the first transistor is a GaN transistor.
A device, comprising: a half bridge circuit including: a high side transistor; and 25 a low side transistor coupled to the high side transistor at an intermediate node; a driver configured to generate a high side driver signal corresponding to a square wave and a low side driver signal corresponding to a square wave, wherein a first deadtime is a period between a falling edge of the low side driver signal and a rising edge of the high side driver signal, wherein the first deadtime includes a first portion and a second portion following the first portion; a half bridge adjustment circuit coupled between the driver and the half bridge circuit and configured to: generate a modified high side driver signal correspond-ing to the high side driver signal with a transition from a low voltage to an intermediate voltage at a beginning of the second portion of the first deadtime and a transition from the intermediate voltage to a high voltage at an end of the first deadtime, wherein the first modified driver signal remains flat at the low voltage during the first portion of the first deadtime; and drive a gate terminal of the high side transistor of a half bridge circuit with the modified high side driver signal, wherein: a second deadtime is a period between a falling edge of the first driver signal and a rising edge of the second driver signal; the half bridge adjustment circuit is configured to generate a modified low side driver signal corre-sponding to the low side driver signal with a transi-tion from the low voltage to the intermediate voltage during the second deadtime and a transition from the intermediate voltage to the high voltage at an end of the second deadtime; and the half bridge adjustment circuit is configured to drive a gate terminal of the low side transistor with the modified low side driver signal.
The device of claim 11, comprising an integrated circuit, wherein the driver and the half bridge adjustment circuit are implemented in the integrated circuit.
The device of claim 11, comprising: 65 a circuit board; and B₂ an integrated circuit including the driver, wherein the integrated circuit, the half bridge adjustment circuit, and the half bridge circuit are mounted to the circuit board.
The device of claim 11, wherein the half bridge adjustment circuit is configured to generate a deadtime signal having a high logic level during the first deadtime and during the second deadtime and having a low logic level outside the first deadtime and the second deadtime, wherein the half bridge adjustment circuit is configured to generate a first deadtime control signal including a first transition during the first deadtime and a second transition at an end of the first deadtime.
A method, comprising: providing a first square wave from a driver to half bridge adjustment circuit coupled between the driver and a half-bridge resonant converter including a high side GaN high electron mobility transistor (HEMT) and a low side GaN HEMT, the first square wave having a high voltage value corresponding to a turn-on voltage of the HEMT and a low voltage value corresponding to a turn-off voltage of the HEMT and having a value less than 0 V; providing a second square wave from the driver to the half bridge adjustment circuit, the first and second square waves having a relative phase that provides a deadtime during which both the first square wave and the second square wave are at the low voltage value; and generating with the half bridge adjustment circuit, a first modified square wave in which the deadtime is divided into a first portion and a second portion, the first modified square wave being at the low voltage value during the first portion and at an intermediate voltage value during the second portion and including a tran-sition from the low voltage value to the intermediate voltage value at a beginning of the second portion of the first deadtime, wherein the first modified driver signal remains flat at the low voltage value during the first portion of the first deadtime; applying the first modified square wave to a gate terminal of the high side GaN HEMT; generating, with the half-bridge adjustment circuit, a second modified square wave in which the deadtime is divided into a first half and a second half, the second modified square wave being at the low voltage value during the first portion and at the intermediate voltage value during the second portion; and applying the second modified square wave to a gate terminal of the low side GaN HEMT.
The method of claim 16, wherein the half bridge adjustment circuit includes a NOR gate configured to receive the first square wave, a comparator coupled to the output of the NOR gate, an AND gate coupled to an output of the NOR gate, and a switch coupled between the AND gate and the gate terminal of the high side GaN HEMT. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
half bridge circuit with GaN transistors
half-bridge resonant converter with GaN HEMTs
Materials described outside the worked examples.
GaN HEMT
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN HEMT gate threshold voltage Vgs(th) | ≤ 2.6 V | GaN |
GaN HEMT turn-off gate voltage Vgs(off) | -10–-3 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 21
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Patent
Atlas literature
Patent
US 12,592,640 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a block diagram of a system 100 including a half bridge circuit and the half bridge adjustment circuit, in accordance with one embodiment.
FIG. 2B. The portion 206 corresponds to the deadtime between times t7 and t8 preceding the rising edge of the second square wave signal 212. 25 In
FIG. 3B. The portion 306 corresponds to the deadtime between times t10 and t12 preceding the rising edge of the low side adjusted driver signal 312. In
FIG. 4A is a schematic diagram of a half bridge adjust- ment circuit, in accordance with one embodiment. 5
FIG. 5 is a cross-sectional view of an HEMT, in accor- dance with one embodiment. 10
FIG. 6 is a flow diagram of a method for operating a half bridge circuit, in accordance with one embodiment.
FIG. 7 is a flow diagram of a method for operating a half bridge circuit, in accordance with one embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: receiving, at a half bridge adjustment circuit, a first driver signal corresponding to a square wave; receiving, at the half bridge adjustment circuit, a second driver signal corresponding to a square wave, wherein a first deadtime is a period between a falling edge of the second driver signal and a rising edge of the first driver signal, wherein the first deadtime includes a first por-tion and a second portion following the first portion; generating, with the half bridge adjustment circuit, a first modified driver signal corresponding to the first driver signal with a transition from a low voltage to an intermediate voltage at a beginning of the second portion of the first deadtime and a transition from the intermediate voltage to a high voltage at an end of the first deadtime, wherein the first modified driver signal remains flat at the low voltage during the first portion of the first deadtime; and driving a gate terminal of a first transistor of a half bridge circuit with the first modified driver signal, wherein a second deadtime is a period between a falling edge of the first driver signal and a rising edge of the second driver signal; generating, with the half bridge adjustment circuit, a second modified driver signal corresponding to the second driver signal with a transition from the low voltage to the intermediate voltage during the second deadtime and a transition from the intermediate voltage to the high voltage at an end of the second deadtime; and driving a gate terminal of a second transistor of the half bridge circuit with the second modified driver signal.
The method of claim 1, generating the first and second driver signals with a driver, wherein the half bridge adjust-ment circuit and the driver are implemented in a same integrated circuit die to the half bridge circuit.
The method of claim 1, generating the first and second driver signals with a driver, wherein the driver is imple-mented in an integrated circuit, wherein the half bridge adjustment circuit is coupled between the integrated circuit and the half bridge circuit.
The method of claim 1, comprising generating, with the half bridge adjustment circuit, a deadtime signal having a high logic level during the first deadtime and during the second deadtime and having a low logic level outside the first deadtime and the second deadtime.
The method of claim 1, wherein the low voltage level is less than 0 V; and wherein the intermediate voltage is 0 V.
The method of claim 1, wherein the first transistor is a GaN transistor.
A device, comprising: a half bridge circuit including: a high side transistor; and 25 a low side transistor coupled to the high side transistor at an intermediate node; a driver configured to generate a high side driver signal corresponding to a square wave and a low side driver signal corresponding to a square wave, wherein a first deadtime is a period between a falling edge of the low side driver signal and a rising edge of the high side driver signal, wherein the first deadtime includes a first portion and a second portion following the first portion; a half bridge adjustment circuit coupled between the driver and the half bridge circuit and configured to: generate a modified high side driver signal correspond-ing to the high side driver signal with a transition from a low voltage to an intermediate voltage at a beginning of the second portion of the first deadtime and a transition from the intermediate voltage to a high voltage at an end of the first deadtime, wherein the first modified driver signal remains flat at the low voltage during the first portion of the first deadtime; and drive a gate terminal of the high side transistor of a half bridge circuit with the modified high side driver signal, wherein: a second deadtime is a period between a falling edge of the first driver signal and a rising edge of the second driver signal; the half bridge adjustment circuit is configured to generate a modified low side driver signal corre-sponding to the low side driver signal with a transi-tion from the low voltage to the intermediate voltage during the second deadtime and a transition from the intermediate voltage to the high voltage at an end of the second deadtime; and the half bridge adjustment circuit is configured to drive a gate terminal of the low side transistor with the modified low side driver signal.
The device of claim 11, comprising an integrated circuit, wherein the driver and the half bridge adjustment circuit are implemented in the integrated circuit.
The device of claim 11, comprising: 65 a circuit board; and B₂ an integrated circuit including the driver, wherein the integrated circuit, the half bridge adjustment circuit, and the half bridge circuit are mounted to the circuit board.
The device of claim 11, wherein the half bridge adjustment circuit is configured to generate a deadtime signal having a high logic level during the first deadtime and during the second deadtime and having a low logic level outside the first deadtime and the second deadtime, wherein the half bridge adjustment circuit is configured to generate a first deadtime control signal including a first transition during the first deadtime and a second transition at an end of the first deadtime.
A method, comprising: providing a first square wave from a driver to half bridge adjustment circuit coupled between the driver and a half-bridge resonant converter including a high side GaN high electron mobility transistor (HEMT) and a low side GaN HEMT, the first square wave having a high voltage value corresponding to a turn-on voltage of the HEMT and a low voltage value corresponding to a turn-off voltage of the HEMT and having a value less than 0 V; providing a second square wave from the driver to the half bridge adjustment circuit, the first and second square waves having a relative phase that provides a deadtime during which both the first square wave and the second square wave are at the low voltage value; and generating with the half bridge adjustment circuit, a first modified square wave in which the deadtime is divided into a first portion and a second portion, the first modified square wave being at the low voltage value during the first portion and at an intermediate voltage value during the second portion and including a tran-sition from the low voltage value to the intermediate voltage value at a beginning of the second portion of the first deadtime, wherein the first modified driver signal remains flat at the low voltage value during the first portion of the first deadtime; applying the first modified square wave to a gate terminal of the high side GaN HEMT; generating, with the half-bridge adjustment circuit, a second modified square wave in which the deadtime is divided into a first half and a second half, the second modified square wave being at the low voltage value during the first portion and at the intermediate voltage value during the second portion; and applying the second modified square wave to a gate terminal of the low side GaN HEMT.
The method of claim 16, wherein the half bridge adjustment circuit includes a NOR gate configured to receive the first square wave, a comparator coupled to the output of the NOR gate, an AND gate coupled to an output of the NOR gate, and a switch coupled between the AND gate and the gate terminal of the high side GaN HEMT. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
half bridge circuit with GaN transistors
half-bridge resonant converter with GaN HEMTs
Materials described outside the worked examples.
GaN HEMT
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN HEMT gate threshold voltage Vgs(th) | ≤ 2.6 V | GaN |
GaN HEMT turn-off gate voltage Vgs(off) | -10–-3 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 21
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Patent
Atlas literature
Patent
US 12,592,640 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a block diagram of a system 100 including a half bridge circuit and the half bridge adjustment circuit, in accordance with one embodiment.
FIG. 2B. The portion 206 corresponds to the deadtime between times t7 and t8 preceding the rising edge of the second square wave signal 212. 25 In
FIG. 3B. The portion 306 corresponds to the deadtime between times t10 and t12 preceding the rising edge of the low side adjusted driver signal 312. In
FIG. 4A is a schematic diagram of a half bridge adjust- ment circuit, in accordance with one embodiment. 5
FIG. 5 is a cross-sectional view of an HEMT, in accor- dance with one embodiment. 10
FIG. 6 is a flow diagram of a method for operating a half bridge circuit, in accordance with one embodiment.
FIG. 7 is a flow diagram of a method for operating a half bridge circuit, in accordance with one embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: receiving, at a half bridge adjustment circuit, a first driver signal corresponding to a square wave; receiving, at the half bridge adjustment circuit, a second driver signal corresponding to a square wave, wherein a first deadtime is a period between a falling edge of the second driver signal and a rising edge of the first driver signal, wherein the first deadtime includes a first por-tion and a second portion following the first portion; generating, with the half bridge adjustment circuit, a first modified driver signal corresponding to the first driver signal with a transition from a low voltage to an intermediate voltage at a beginning of the second portion of the first deadtime and a transition from the intermediate voltage to a high voltage at an end of the first deadtime, wherein the first modified driver signal remains flat at the low voltage during the first portion of the first deadtime; and driving a gate terminal of a first transistor of a half bridge circuit with the first modified driver signal, wherein a second deadtime is a period between a falling edge of the first driver signal and a rising edge of the second driver signal; generating, with the half bridge adjustment circuit, a second modified driver signal corresponding to the second driver signal with a transition from the low voltage to the intermediate voltage during the second deadtime and a transition from the intermediate voltage to the high voltage at an end of the second deadtime; and driving a gate terminal of a second transistor of the half bridge circuit with the second modified driver signal.
The method of claim 1, generating the first and second driver signals with a driver, wherein the half bridge adjust-ment circuit and the driver are implemented in a same integrated circuit die to the half bridge circuit.
The method of claim 1, generating the first and second driver signals with a driver, wherein the driver is imple-mented in an integrated circuit, wherein the half bridge adjustment circuit is coupled between the integrated circuit and the half bridge circuit.
The method of claim 1, comprising generating, with the half bridge adjustment circuit, a deadtime signal having a high logic level during the first deadtime and during the second deadtime and having a low logic level outside the first deadtime and the second deadtime.
The method of claim 1, wherein the low voltage level is less than 0 V; and wherein the intermediate voltage is 0 V.
The method of claim 1, wherein the first transistor is a GaN transistor.
A device, comprising: a half bridge circuit including: a high side transistor; and 25 a low side transistor coupled to the high side transistor at an intermediate node; a driver configured to generate a high side driver signal corresponding to a square wave and a low side driver signal corresponding to a square wave, wherein a first deadtime is a period between a falling edge of the low side driver signal and a rising edge of the high side driver signal, wherein the first deadtime includes a first portion and a second portion following the first portion; a half bridge adjustment circuit coupled between the driver and the half bridge circuit and configured to: generate a modified high side driver signal correspond-ing to the high side driver signal with a transition from a low voltage to an intermediate voltage at a beginning of the second portion of the first deadtime and a transition from the intermediate voltage to a high voltage at an end of the first deadtime, wherein the first modified driver signal remains flat at the low voltage during the first portion of the first deadtime; and drive a gate terminal of the high side transistor of a half bridge circuit with the modified high side driver signal, wherein: a second deadtime is a period between a falling edge of the first driver signal and a rising edge of the second driver signal; the half bridge adjustment circuit is configured to generate a modified low side driver signal corre-sponding to the low side driver signal with a transi-tion from the low voltage to the intermediate voltage during the second deadtime and a transition from the intermediate voltage to the high voltage at an end of the second deadtime; and the half bridge adjustment circuit is configured to drive a gate terminal of the low side transistor with the modified low side driver signal.
The device of claim 11, comprising an integrated circuit, wherein the driver and the half bridge adjustment circuit are implemented in the integrated circuit.
The device of claim 11, comprising: 65 a circuit board; and B₂ an integrated circuit including the driver, wherein the integrated circuit, the half bridge adjustment circuit, and the half bridge circuit are mounted to the circuit board.
The device of claim 11, wherein the half bridge adjustment circuit is configured to generate a deadtime signal having a high logic level during the first deadtime and during the second deadtime and having a low logic level outside the first deadtime and the second deadtime, wherein the half bridge adjustment circuit is configured to generate a first deadtime control signal including a first transition during the first deadtime and a second transition at an end of the first deadtime.
A method, comprising: providing a first square wave from a driver to half bridge adjustment circuit coupled between the driver and a half-bridge resonant converter including a high side GaN high electron mobility transistor (HEMT) and a low side GaN HEMT, the first square wave having a high voltage value corresponding to a turn-on voltage of the HEMT and a low voltage value corresponding to a turn-off voltage of the HEMT and having a value less than 0 V; providing a second square wave from the driver to the half bridge adjustment circuit, the first and second square waves having a relative phase that provides a deadtime during which both the first square wave and the second square wave are at the low voltage value; and generating with the half bridge adjustment circuit, a first modified square wave in which the deadtime is divided into a first portion and a second portion, the first modified square wave being at the low voltage value during the first portion and at an intermediate voltage value during the second portion and including a tran-sition from the low voltage value to the intermediate voltage value at a beginning of the second portion of the first deadtime, wherein the first modified driver signal remains flat at the low voltage value during the first portion of the first deadtime; applying the first modified square wave to a gate terminal of the high side GaN HEMT; generating, with the half-bridge adjustment circuit, a second modified square wave in which the deadtime is divided into a first half and a second half, the second modified square wave being at the low voltage value during the first portion and at the intermediate voltage value during the second portion; and applying the second modified square wave to a gate terminal of the low side GaN HEMT.
The method of claim 16, wherein the half bridge adjustment circuit includes a NOR gate configured to receive the first square wave, a comparator coupled to the output of the NOR gate, an AND gate coupled to an output of the NOR gate, and a switch coupled between the AND gate and the gate terminal of the high side GaN HEMT. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
half bridge circuit with GaN transistors
half-bridge resonant converter with GaN HEMTs
Materials described outside the worked examples.
GaN HEMT
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN HEMT gate threshold voltage Vgs(th) | ≤ 2.6 V | GaN |
GaN HEMT turn-off gate voltage Vgs(off) | -10–-3 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 21
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,592,640 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a block diagram of a system 100 including a half bridge circuit and the half bridge adjustment circuit, in accordance with one embodiment.
FIG. 2B. The portion 206 corresponds to the deadtime between times t7 and t8 preceding the rising edge of the second square wave signal 212. 25 In
FIG. 3B. The portion 306 corresponds to the deadtime between times t10 and t12 preceding the rising edge of the low side adjusted driver signal 312. In
FIG. 4A is a schematic diagram of a half bridge adjust- ment circuit, in accordance with one embodiment. 5
FIG. 5 is a cross-sectional view of an HEMT, in accor- dance with one embodiment. 10
FIG. 6 is a flow diagram of a method for operating a half bridge circuit, in accordance with one embodiment.
FIG. 7 is a flow diagram of a method for operating a half bridge circuit, in accordance with one embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: receiving, at a half bridge adjustment circuit, a first driver signal corresponding to a square wave; receiving, at the half bridge adjustment circuit, a second driver signal corresponding to a square wave, wherein a first deadtime is a period between a falling edge of the second driver signal and a rising edge of the first driver signal, wherein the first deadtime includes a first por-tion and a second portion following the first portion; generating, with the half bridge adjustment circuit, a first modified driver signal corresponding to the first driver signal with a transition from a low voltage to an intermediate voltage at a beginning of the second portion of the first deadtime and a transition from the intermediate voltage to a high voltage at an end of the first deadtime, wherein the first modified driver signal remains flat at the low voltage during the first portion of the first deadtime; and driving a gate terminal of a first transistor of a half bridge circuit with the first modified driver signal, wherein a second deadtime is a period between a falling edge of the first driver signal and a rising edge of the second driver signal; generating, with the half bridge adjustment circuit, a second modified driver signal corresponding to the second driver signal with a transition from the low voltage to the intermediate voltage during the second deadtime and a transition from the intermediate voltage to the high voltage at an end of the second deadtime; and driving a gate terminal of a second transistor of the half bridge circuit with the second modified driver signal.
The method of claim 1, generating the first and second driver signals with a driver, wherein the half bridge adjust-ment circuit and the driver are implemented in a same integrated circuit die to the half bridge circuit.
The method of claim 1, generating the first and second driver signals with a driver, wherein the driver is imple-mented in an integrated circuit, wherein the half bridge adjustment circuit is coupled between the integrated circuit and the half bridge circuit.
The method of claim 1, comprising generating, with the half bridge adjustment circuit, a deadtime signal having a high logic level during the first deadtime and during the second deadtime and having a low logic level outside the first deadtime and the second deadtime.
The method of claim 1, wherein the low voltage level is less than 0 V; and wherein the intermediate voltage is 0 V.
The method of claim 1, wherein the first transistor is a GaN transistor.
A device, comprising: a half bridge circuit including: a high side transistor; and 25 a low side transistor coupled to the high side transistor at an intermediate node; a driver configured to generate a high side driver signal corresponding to a square wave and a low side driver signal corresponding to a square wave, wherein a first deadtime is a period between a falling edge of the low side driver signal and a rising edge of the high side driver signal, wherein the first deadtime includes a first portion and a second portion following the first portion; a half bridge adjustment circuit coupled between the driver and the half bridge circuit and configured to: generate a modified high side driver signal correspond-ing to the high side driver signal with a transition from a low voltage to an intermediate voltage at a beginning of the second portion of the first deadtime and a transition from the intermediate voltage to a high voltage at an end of the first deadtime, wherein the first modified driver signal remains flat at the low voltage during the first portion of the first deadtime; and drive a gate terminal of the high side transistor of a half bridge circuit with the modified high side driver signal, wherein: a second deadtime is a period between a falling edge of the first driver signal and a rising edge of the second driver signal; the half bridge adjustment circuit is configured to generate a modified low side driver signal corre-sponding to the low side driver signal with a transi-tion from the low voltage to the intermediate voltage during the second deadtime and a transition from the intermediate voltage to the high voltage at an end of the second deadtime; and the half bridge adjustment circuit is configured to drive a gate terminal of the low side transistor with the modified low side driver signal.
The device of claim 11, comprising an integrated circuit, wherein the driver and the half bridge adjustment circuit are implemented in the integrated circuit.
The device of claim 11, comprising: 65 a circuit board; and B₂ an integrated circuit including the driver, wherein the integrated circuit, the half bridge adjustment circuit, and the half bridge circuit are mounted to the circuit board.
The device of claim 11, wherein the half bridge adjustment circuit is configured to generate a deadtime signal having a high logic level during the first deadtime and during the second deadtime and having a low logic level outside the first deadtime and the second deadtime, wherein the half bridge adjustment circuit is configured to generate a first deadtime control signal including a first transition during the first deadtime and a second transition at an end of the first deadtime.
A method, comprising: providing a first square wave from a driver to half bridge adjustment circuit coupled between the driver and a half-bridge resonant converter including a high side GaN high electron mobility transistor (HEMT) and a low side GaN HEMT, the first square wave having a high voltage value corresponding to a turn-on voltage of the HEMT and a low voltage value corresponding to a turn-off voltage of the HEMT and having a value less than 0 V; providing a second square wave from the driver to the half bridge adjustment circuit, the first and second square waves having a relative phase that provides a deadtime during which both the first square wave and the second square wave are at the low voltage value; and generating with the half bridge adjustment circuit, a first modified square wave in which the deadtime is divided into a first portion and a second portion, the first modified square wave being at the low voltage value during the first portion and at an intermediate voltage value during the second portion and including a tran-sition from the low voltage value to the intermediate voltage value at a beginning of the second portion of the first deadtime, wherein the first modified driver signal remains flat at the low voltage value during the first portion of the first deadtime; applying the first modified square wave to a gate terminal of the high side GaN HEMT; generating, with the half-bridge adjustment circuit, a second modified square wave in which the deadtime is divided into a first half and a second half, the second modified square wave being at the low voltage value during the first portion and at the intermediate voltage value during the second portion; and applying the second modified square wave to a gate terminal of the low side GaN HEMT.
The method of claim 16, wherein the half bridge adjustment circuit includes a NOR gate configured to receive the first square wave, a comparator coupled to the output of the NOR gate, an AND gate coupled to an output of the NOR gate, and a switch coupled between the AND gate and the gate terminal of the high side GaN HEMT. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
half bridge circuit with GaN transistors
half-bridge resonant converter with GaN HEMTs
Materials described outside the worked examples.
GaN HEMT
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN HEMT gate threshold voltage Vgs(th) | ≤ 2.6 V | GaN |
GaN HEMT turn-off gate voltage Vgs(off) | -10–-3 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 21
Related documents with shared materials, methods, properties, or citations.
Thickness | 50–300 nm | — |
Thickness | 50–150 nm | — |
Thickness | 30–70 nm | — |
Thickness | 20–50 nm | — |
Voltage | ≤ 0 V | — |
Voltage | ≥ 600 V | — |
Cited non-patent literature · 3
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
Thickness | 50–300 nm | — |
Thickness | 50–150 nm | — |
Thickness | 30–70 nm | — |
Thickness | 20–50 nm | — |
Voltage | ≤ 0 V | — |
Voltage | ≥ 600 V | — |
Cited non-patent literature · 3
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
Thickness | 50–300 nm | — |
Thickness | 50–150 nm | — |
Thickness | 30–70 nm | — |
Thickness | 20–50 nm | — |
Voltage | ≤ 0 V | — |
Voltage | ≥ 600 V | — |
Cited non-patent literature · 3
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
Thickness | 50–300 nm | — |
Thickness | 50–150 nm | — |
Thickness | 30–70 nm | — |
Thickness | 20–50 nm | — |
Voltage | ≤ 0 V | — |
Voltage | ≥ 600 V | — |
Cited non-patent literature · 3
