Research paperExperimental CharacterizationLarge-Scale Integrated Vector-Matrix Multiplication Processor Based on Monolayer MoS₂Guilherme Migliato Marega, Hyun Goo Ji, Zhenyu Wang, Mukesh Tripathi et al.2023·10.1038/s41928-023-01064-1·arXiv:2303.07183
Wafer-scale 32×32 floating-gate field-effect transistor matrix chip using monolayer MoS₂ channels and Pt/HfO₂ floating-gate stack with Cr/Pt gate and Ti/Au source-drain contacts.1 characterization1 property2 figuresExperimentalMoS₂Studied MaterialHfO₂Substrate / DielectricPtCapping Or ContactCrCapping Or ContactAuCapping Or ContactTiCapping Or ContactExpand
Research paperExperimental CharacterizationLarge-Scale Integrated Vector-Matrix Multiplication Processor Based on Monolayer MoS₂Guilherme Migliato Marega, Hyun Goo Ji, Zhenyu Wang, Mukesh Tripathi et al.2023·10.1038/s41928-023-01064-1·arXiv:2303.07183
Wafer-scale 32×32 floating-gate field-effect transistor matrix chip using monolayer MoS₂ channels and Pt/HfO₂ floating-gate stack with Cr/Pt gate and Ti/Au source-drain contacts.1 characterization1 property2 figuresExperimentalMoS₂Studied MaterialHfO₂Substrate / DielectricPtCapping Or ContactCrCapping Or ContactAuCapping Or ContactTiCapping Or ContactExpand
Research paperExperimental CharacterizationLarge-Scale Integrated Vector-Matrix Multiplication Processor Based on Monolayer MoS₂Guilherme Migliato Marega, Hyun Goo Ji, Zhenyu Wang, Mukesh Tripathi et al.2023·10.1038/s41928-023-01064-1·arXiv:2303.07183
Wafer-scale 32×32 floating-gate field-effect transistor matrix chip using monolayer MoS₂ channels and Pt/HfO₂ floating-gate stack with Cr/Pt gate and Ti/Au source-drain contacts.1 characterization1 property2 figuresExperimentalMoS₂Studied MaterialHfO₂Substrate / DielectricPtCapping Or ContactCrCapping Or ContactAuCapping Or ContactTiCapping Or ContactExpand
Research paperExperimental CharacterizationLarge-Scale Integrated Vector-Matrix Multiplication Processor Based on Monolayer MoS₂Guilherme Migliato Marega, Hyun Goo Ji, Zhenyu Wang, Mukesh Tripathi et al.2023·10.1038/s41928-023-01064-1·arXiv:2303.07183
Wafer-scale 32×32 floating-gate field-effect transistor matrix chip using monolayer MoS₂ channels and Pt/HfO₂ floating-gate stack with Cr/Pt gate and Ti/Au source-drain contacts.1 characterization1 property2 figuresExperimentalMoS₂Studied MaterialHfO₂Substrate / DielectricPtCapping Or ContactCrCapping Or ContactAuCapping Or ContactTiCapping Or ContactExpand