Patent
Atlas literature
Patent
US 12,038,469 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a circuit diagram of an intermittent oper- ating life (IOL) testing system and how it is connected to a GaN-based device under test (DUT) …
FIG. 2 depicts a circuit diagram of an intermittent oper- 15 ating life (IOL) testing system and how it is connected to a GaN-based device under test (DUT) …
FIG. 3 depicts a flowchart of a method for operating a testing system for measuring an intermittent operating life 20 (IOL) of a GaN-based device according to …
FIG. 4 depicts signal waveforms of operation of the testing system 10 according to some embodiments of the subject application. 25
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A system for measuring an intermittent operating life (IOL) of a GaN-based device under test (DUT), the system being operable in a stressing mode, a cooling mode, and a measure mode, the system being operable in the stressing mode, the measure mode, the cooling mode, and the measure mode in sequence, and comprising: 30 a controlling circuit configured for detecting a signal VDIM from a drain terminal of the DUT and a signal VSIM from a source terminal of the DUT and comput-ing a drain-source resistance Rds of the DUT when the system is operated in the measure mode; 35 a stressing circuit configured for applying a regulated stressing power Pstr to the DUT to increase a junction temperature of the DUT to an ON-junction temperature TjON when the system is operated in the stressing mode, wherein the regulated stressing power Pstr is given by Pstr=Idsstr*Vdsstr, where Idsstr is a regulated drain-source current passing through the DUT and Vdsstr is a regulated drain-source voltage Vdsstr across the DUT; a cooling circuit configured for, after the DUT is turned off, cooling the DUT to decrease the junction tempera-ture of the DUT to an OFF junction temperature TjOFF; a gate-bias circuit configured to receive a control signal VGM from the controlling circuit to turn on the DUT when the system is operated in the measure mode; and receive a control signal VGOFF from the controlling circuit to turn off the DUT when the system is operated in the cooling mode; and a measure-bias circuit configured to receive, after the DUT is turned on, a reference signal IMCtrl from the controlling circuit and supply a regulated drain-source current Idsmea to the DUT when the system is operated in the measure mode, such that the controlling circuit computes the drain-source resistance Rds of the DUT; wherein the controlling circuit is further configured to determine the drain-source resistance Rds to be an ON-drain-source resistance RdsON of the DUT if the drain-source resistance Rds is obtained when the junction temperature of the DUT reaches the ON-junction tem-perature TjON; and determine the drain-source resistance Rds to be an OFF-drain-source resistance RdsOFF of the DUT if the B₂ drain-source resistance Rds is obtained when the junc-tion temperature of the DUT reaches the OFF junction temperature TjOFF; wherein the gate-bias circuit comprises a gate-bias power supply PSVG and a first switching device M₁ con-nected to the gate-bias power supply PSVG; an end of the first switching device M₁ is connected to the gate-bias power supply PSVG, and another end of the first switching device M₁ is connected to a VG node; the VG node is connected to a gate of the DUT; the controlling circuit is configured to control the first switching device M₁ to connect the gate-bias power supply PSVG to the VG node to turn on the DUT when the system is operated in the measure mode; wherein the gate-bias circuit further comprises a third switching device M3; an end of the third switching device M₃ is connected to a ground GND, and another end of the third switching device M₃ is connected to the VG node; the third switching device M₃ is configured to receive a control signal VGOFF from the control-ling circuit to connect the ground GND to the VG node to turn off the DUT.
The system according to claim 1, wherein the TjON is given by TjON=Pstr×Rth(j-a)+Ta, where Ta is an ambient temperature and Rth(j-a) is a junction thermal resistance of the DUT at the ambient temperature Ta.
The system according to claim 1, wherein the OFF junction temperature TjOFF is given by TjOFF=Ta, where Ta is an ambient temperature.
The system according to claim 1, wherein the stressing circuit is further configured to: receive a first reference signal VdsCtrl and a second reference signal IdsCtrl from the controlling circuit; detect the signal VDIM from the drain terminal of the DUT and the signal VSIM from the source terminal of the DUT; control a voltage applied to the drain terminal of the DUT based on the received first reference signals VdsCtrl and the detected signal VDIM to regulate the drain-source voltage Vdsstr to be equal to VdsCtrl; and control a voltage applied to the VG node based on the received second reference signals IdsCtrl and the detected signal VSIM to regulate the drain-source cur-rent Idsstr to be equal to IdsCtrl. R₁
The system according to claim 1, further comprising a fourth diode D₄ having a cathode coupled to the drain terminal of the DUT, and configured for allowing the drain-source current Idsstr flowing only in one direction from the stressing circuit to the drain terminal of the DUT.
The system according to claim 1, further comprising a fifth diode D₅ having a cathode connected to the drain terminal of the DUT and configured for allowing the drain-source current Idsmea flowing only in one direction from the measure-bias circuit to the drain terminal of the DUT.
The system according to claim 1, wherein the cooling circuit comprises a fan configured to receive a control signal AirCtrl from the controlling circuit and generate a flow of air surrounding the DUT to cool down the DUT.
The system according to claim 1, further comprising 30 a man-machine interfacing unit configured for facilitating a user to select and set up operation modes and displaying operation setting menus and measurement results.
The system according to claim 1, further comprising a storage unit configured for storing operation setting param-eters and measurement results.
A method for measuring an intermittent operating life (IOL) of a GaN-based devices under test (DUT) having a source terminal, a drain terminal, and a gate terminal, the method comprising: stressing, by a stressing circuit, the DUT by applying a regulated stressing power Pstr to the DUT to increase a junction temperature of the DUT to an ON-junction temperature TjON; wherein the regulated stressing power Pstr is given by Pstr=Idsstr*Vdsstr, where Idsstr is a regulated drain-source current Idsstr passing through the DUT, and Vdsstr is a regulated drain-source voltage across the DUT; measuring, by a controlling circuit, a drain-source resistance Rds of the DUT and determining the drain-source resistance Rds to be an ON-drain-source resis-tance RdsON of the DUT when the junction tempera-ture of the DUT reaches the ON-junction temperature TjON; cooling, by a cooling circuit, the DUT to decrease the junction temperature of the DUT to an OFF junction temperature TjOFF; and measuring, by the controlling circuit, the drain-source resistance Rds of the DUT and determining the drain-source resistance Rds to be an OFF-drain-source resistance RdsOFF of the DUT when the junction temperature of the DUT reaches the OFF junction temperature TjOFF.
The method according to claim 14, wherein the TjON is given by TjON=Pstr×Rth(j-a)+Ta, where Ta is an ambient temperature and Rth(j-a) a junction thermal resistance of the DUT at the ambient temperature Ta.
The method according to claim 14, wherein the OFF-junction temperature TjOFF is given by TjOFF=Ta where Ta is an ambient temperature.
The method according to claim 14, wherein the step of stressing the DUT comprises: switching off, by the controlling circuit, a sixth switching device M₆ to block any current flowing from a mea-sure-bias circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a fourth switching device M₄ to allow a drain-source current Idsstr flow-ing from the stressing circuit to the drain terminal of the DUT; receiving, by the stressing circuit, a reference signal IdsCtrl from the controlling circuit; regulating, by the stressing unit circuit, the drain-source current Idsstr passing through the DUT based on the reference signal IdsCtrl; receiving, by the stressing circuit, a reference signal VdsCtrl from the controlling circuit; and regulating, by the stressing circuit, a drain-source voltage Vdsstr applied across the DUT based on the reference signal VdsCtrl.
The method according to claim 14, wherein the step of measuring the ON-drain-source resistance RdsON of the DUT comprises: switching off, by the controlling circuit, a fourth switch-ing device M₄ to block any current flowing from the stressing circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a sixth switching device M₆ to allow a drain-source current Idsmea flowing from a measure-bias circuit to the drain termi-nal of the DUT; switching on, by the controlling circuit, a first switching device M₁ to connect the gate terminal of the DUT to a power supply PSVG to turn on the DUT; receiving, by the measure-bias circuit, a reference signal IMCtrl from the controlling circuit; regulating, by the measure-bias circuit, the drain-source current Idsmea based on the received reference signal IMCtrl; receiving, by the controlling circuit, a signal VDIM from the drain terminal of the DUT and a signal VSIM from the source terminal of the DUT; and determining, by the controlling circuit, the ON-drain-source resistance RdsON of the DUT, wherein RdsON is given by R1×(VDIM-VSIM) RdsON =; VSIM where R₁ is a resistor connected between the source termi-nal of the DUT and a ground GND.
The method according to claim 14, wherein the step of cooling the DUT comprises: switching off, by the controlling circuit, a sixth switching device M₆ to block any current flowing from the measure-bias circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a third switching device M₃ to connect the gate terminal of the DUT to a ground GND to turn off the DUT; and turning on, by the controlling circuit, a fan to cool down the DUT for a preset period of time.
The method according to claim 14, wherein the step of measuring the OFF-drain-source resistance RdsOFF of the DUT comprises: 19 switching off, by the controlling circuit, a fourth switch-ing device M₄ to block any current flowing from the stressing circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a sixth switching device M₆ to allow a drain-source current Idsmea flowing from a measure-bias circuit to the drain termi-nal of the DUT; switching on, by the controlling circuit, a first switching device M₁ to connect the gate terminal of the DUT to a power supply PSVG to turn on the DUT; receiving, by the measure-bias circuit, a reference signal IMCtrl from the controlling circuit; regulating, by the measure-bias circuit, the drain-source current Idsmea based on the received reference signal IMCtrl; receiving, by the controlling circuit, a signal VDIM from the drain terminal of the DUT and a signal VSIM from the source terminal of the DUT; and determining, by the controlling circuit, the OFF-drain-source resistance RdsOFF of the DUT, wherein RdsOFF is given by R1×(VDIM-VSIM) RdsOFF =; VSIM where R₁ is a resistor connected between the source termi-nal of the DUT and a ground GND. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based device under test (DUT)
No layer stack recorded.
Materials described outside the worked examples.
GaN
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 14
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,038,469 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a circuit diagram of an intermittent oper- ating life (IOL) testing system and how it is connected to a GaN-based device under test (DUT) …
FIG. 2 depicts a circuit diagram of an intermittent oper- 15 ating life (IOL) testing system and how it is connected to a GaN-based device under test (DUT) …
FIG. 3 depicts a flowchart of a method for operating a testing system for measuring an intermittent operating life 20 (IOL) of a GaN-based device according to …
FIG. 4 depicts signal waveforms of operation of the testing system 10 according to some embodiments of the subject application. 25
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A system for measuring an intermittent operating life (IOL) of a GaN-based device under test (DUT), the system being operable in a stressing mode, a cooling mode, and a measure mode, the system being operable in the stressing mode, the measure mode, the cooling mode, and the measure mode in sequence, and comprising: 30 a controlling circuit configured for detecting a signal VDIM from a drain terminal of the DUT and a signal VSIM from a source terminal of the DUT and comput-ing a drain-source resistance Rds of the DUT when the system is operated in the measure mode; 35 a stressing circuit configured for applying a regulated stressing power Pstr to the DUT to increase a junction temperature of the DUT to an ON-junction temperature TjON when the system is operated in the stressing mode, wherein the regulated stressing power Pstr is given by Pstr=Idsstr*Vdsstr, where Idsstr is a regulated drain-source current passing through the DUT and Vdsstr is a regulated drain-source voltage Vdsstr across the DUT; a cooling circuit configured for, after the DUT is turned off, cooling the DUT to decrease the junction tempera-ture of the DUT to an OFF junction temperature TjOFF; a gate-bias circuit configured to receive a control signal VGM from the controlling circuit to turn on the DUT when the system is operated in the measure mode; and receive a control signal VGOFF from the controlling circuit to turn off the DUT when the system is operated in the cooling mode; and a measure-bias circuit configured to receive, after the DUT is turned on, a reference signal IMCtrl from the controlling circuit and supply a regulated drain-source current Idsmea to the DUT when the system is operated in the measure mode, such that the controlling circuit computes the drain-source resistance Rds of the DUT; wherein the controlling circuit is further configured to determine the drain-source resistance Rds to be an ON-drain-source resistance RdsON of the DUT if the drain-source resistance Rds is obtained when the junction temperature of the DUT reaches the ON-junction tem-perature TjON; and determine the drain-source resistance Rds to be an OFF-drain-source resistance RdsOFF of the DUT if the B₂ drain-source resistance Rds is obtained when the junc-tion temperature of the DUT reaches the OFF junction temperature TjOFF; wherein the gate-bias circuit comprises a gate-bias power supply PSVG and a first switching device M₁ con-nected to the gate-bias power supply PSVG; an end of the first switching device M₁ is connected to the gate-bias power supply PSVG, and another end of the first switching device M₁ is connected to a VG node; the VG node is connected to a gate of the DUT; the controlling circuit is configured to control the first switching device M₁ to connect the gate-bias power supply PSVG to the VG node to turn on the DUT when the system is operated in the measure mode; wherein the gate-bias circuit further comprises a third switching device M3; an end of the third switching device M₃ is connected to a ground GND, and another end of the third switching device M₃ is connected to the VG node; the third switching device M₃ is configured to receive a control signal VGOFF from the control-ling circuit to connect the ground GND to the VG node to turn off the DUT.
The system according to claim 1, wherein the TjON is given by TjON=Pstr×Rth(j-a)+Ta, where Ta is an ambient temperature and Rth(j-a) is a junction thermal resistance of the DUT at the ambient temperature Ta.
The system according to claim 1, wherein the OFF junction temperature TjOFF is given by TjOFF=Ta, where Ta is an ambient temperature.
The system according to claim 1, wherein the stressing circuit is further configured to: receive a first reference signal VdsCtrl and a second reference signal IdsCtrl from the controlling circuit; detect the signal VDIM from the drain terminal of the DUT and the signal VSIM from the source terminal of the DUT; control a voltage applied to the drain terminal of the DUT based on the received first reference signals VdsCtrl and the detected signal VDIM to regulate the drain-source voltage Vdsstr to be equal to VdsCtrl; and control a voltage applied to the VG node based on the received second reference signals IdsCtrl and the detected signal VSIM to regulate the drain-source cur-rent Idsstr to be equal to IdsCtrl. R₁
The system according to claim 1, further comprising a fourth diode D₄ having a cathode coupled to the drain terminal of the DUT, and configured for allowing the drain-source current Idsstr flowing only in one direction from the stressing circuit to the drain terminal of the DUT.
The system according to claim 1, further comprising a fifth diode D₅ having a cathode connected to the drain terminal of the DUT and configured for allowing the drain-source current Idsmea flowing only in one direction from the measure-bias circuit to the drain terminal of the DUT.
The system according to claim 1, wherein the cooling circuit comprises a fan configured to receive a control signal AirCtrl from the controlling circuit and generate a flow of air surrounding the DUT to cool down the DUT.
The system according to claim 1, further comprising 30 a man-machine interfacing unit configured for facilitating a user to select and set up operation modes and displaying operation setting menus and measurement results.
The system according to claim 1, further comprising a storage unit configured for storing operation setting param-eters and measurement results.
A method for measuring an intermittent operating life (IOL) of a GaN-based devices under test (DUT) having a source terminal, a drain terminal, and a gate terminal, the method comprising: stressing, by a stressing circuit, the DUT by applying a regulated stressing power Pstr to the DUT to increase a junction temperature of the DUT to an ON-junction temperature TjON; wherein the regulated stressing power Pstr is given by Pstr=Idsstr*Vdsstr, where Idsstr is a regulated drain-source current Idsstr passing through the DUT, and Vdsstr is a regulated drain-source voltage across the DUT; measuring, by a controlling circuit, a drain-source resistance Rds of the DUT and determining the drain-source resistance Rds to be an ON-drain-source resis-tance RdsON of the DUT when the junction tempera-ture of the DUT reaches the ON-junction temperature TjON; cooling, by a cooling circuit, the DUT to decrease the junction temperature of the DUT to an OFF junction temperature TjOFF; and measuring, by the controlling circuit, the drain-source resistance Rds of the DUT and determining the drain-source resistance Rds to be an OFF-drain-source resistance RdsOFF of the DUT when the junction temperature of the DUT reaches the OFF junction temperature TjOFF.
The method according to claim 14, wherein the TjON is given by TjON=Pstr×Rth(j-a)+Ta, where Ta is an ambient temperature and Rth(j-a) a junction thermal resistance of the DUT at the ambient temperature Ta.
The method according to claim 14, wherein the OFF-junction temperature TjOFF is given by TjOFF=Ta where Ta is an ambient temperature.
The method according to claim 14, wherein the step of stressing the DUT comprises: switching off, by the controlling circuit, a sixth switching device M₆ to block any current flowing from a mea-sure-bias circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a fourth switching device M₄ to allow a drain-source current Idsstr flow-ing from the stressing circuit to the drain terminal of the DUT; receiving, by the stressing circuit, a reference signal IdsCtrl from the controlling circuit; regulating, by the stressing unit circuit, the drain-source current Idsstr passing through the DUT based on the reference signal IdsCtrl; receiving, by the stressing circuit, a reference signal VdsCtrl from the controlling circuit; and regulating, by the stressing circuit, a drain-source voltage Vdsstr applied across the DUT based on the reference signal VdsCtrl.
The method according to claim 14, wherein the step of measuring the ON-drain-source resistance RdsON of the DUT comprises: switching off, by the controlling circuit, a fourth switch-ing device M₄ to block any current flowing from the stressing circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a sixth switching device M₆ to allow a drain-source current Idsmea flowing from a measure-bias circuit to the drain termi-nal of the DUT; switching on, by the controlling circuit, a first switching device M₁ to connect the gate terminal of the DUT to a power supply PSVG to turn on the DUT; receiving, by the measure-bias circuit, a reference signal IMCtrl from the controlling circuit; regulating, by the measure-bias circuit, the drain-source current Idsmea based on the received reference signal IMCtrl; receiving, by the controlling circuit, a signal VDIM from the drain terminal of the DUT and a signal VSIM from the source terminal of the DUT; and determining, by the controlling circuit, the ON-drain-source resistance RdsON of the DUT, wherein RdsON is given by R1×(VDIM-VSIM) RdsON =; VSIM where R₁ is a resistor connected between the source termi-nal of the DUT and a ground GND.
The method according to claim 14, wherein the step of cooling the DUT comprises: switching off, by the controlling circuit, a sixth switching device M₆ to block any current flowing from the measure-bias circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a third switching device M₃ to connect the gate terminal of the DUT to a ground GND to turn off the DUT; and turning on, by the controlling circuit, a fan to cool down the DUT for a preset period of time.
The method according to claim 14, wherein the step of measuring the OFF-drain-source resistance RdsOFF of the DUT comprises: 19 switching off, by the controlling circuit, a fourth switch-ing device M₄ to block any current flowing from the stressing circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a sixth switching device M₆ to allow a drain-source current Idsmea flowing from a measure-bias circuit to the drain termi-nal of the DUT; switching on, by the controlling circuit, a first switching device M₁ to connect the gate terminal of the DUT to a power supply PSVG to turn on the DUT; receiving, by the measure-bias circuit, a reference signal IMCtrl from the controlling circuit; regulating, by the measure-bias circuit, the drain-source current Idsmea based on the received reference signal IMCtrl; receiving, by the controlling circuit, a signal VDIM from the drain terminal of the DUT and a signal VSIM from the source terminal of the DUT; and determining, by the controlling circuit, the OFF-drain-source resistance RdsOFF of the DUT, wherein RdsOFF is given by R1×(VDIM-VSIM) RdsOFF =; VSIM where R₁ is a resistor connected between the source termi-nal of the DUT and a ground GND. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based device under test (DUT)
No layer stack recorded.
Materials described outside the worked examples.
GaN
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 14
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,038,469 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a circuit diagram of an intermittent oper- ating life (IOL) testing system and how it is connected to a GaN-based device under test (DUT) …
FIG. 2 depicts a circuit diagram of an intermittent oper- 15 ating life (IOL) testing system and how it is connected to a GaN-based device under test (DUT) …
FIG. 3 depicts a flowchart of a method for operating a testing system for measuring an intermittent operating life 20 (IOL) of a GaN-based device according to …
FIG. 4 depicts signal waveforms of operation of the testing system 10 according to some embodiments of the subject application. 25
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A system for measuring an intermittent operating life (IOL) of a GaN-based device under test (DUT), the system being operable in a stressing mode, a cooling mode, and a measure mode, the system being operable in the stressing mode, the measure mode, the cooling mode, and the measure mode in sequence, and comprising: 30 a controlling circuit configured for detecting a signal VDIM from a drain terminal of the DUT and a signal VSIM from a source terminal of the DUT and comput-ing a drain-source resistance Rds of the DUT when the system is operated in the measure mode; 35 a stressing circuit configured for applying a regulated stressing power Pstr to the DUT to increase a junction temperature of the DUT to an ON-junction temperature TjON when the system is operated in the stressing mode, wherein the regulated stressing power Pstr is given by Pstr=Idsstr*Vdsstr, where Idsstr is a regulated drain-source current passing through the DUT and Vdsstr is a regulated drain-source voltage Vdsstr across the DUT; a cooling circuit configured for, after the DUT is turned off, cooling the DUT to decrease the junction tempera-ture of the DUT to an OFF junction temperature TjOFF; a gate-bias circuit configured to receive a control signal VGM from the controlling circuit to turn on the DUT when the system is operated in the measure mode; and receive a control signal VGOFF from the controlling circuit to turn off the DUT when the system is operated in the cooling mode; and a measure-bias circuit configured to receive, after the DUT is turned on, a reference signal IMCtrl from the controlling circuit and supply a regulated drain-source current Idsmea to the DUT when the system is operated in the measure mode, such that the controlling circuit computes the drain-source resistance Rds of the DUT; wherein the controlling circuit is further configured to determine the drain-source resistance Rds to be an ON-drain-source resistance RdsON of the DUT if the drain-source resistance Rds is obtained when the junction temperature of the DUT reaches the ON-junction tem-perature TjON; and determine the drain-source resistance Rds to be an OFF-drain-source resistance RdsOFF of the DUT if the B₂ drain-source resistance Rds is obtained when the junc-tion temperature of the DUT reaches the OFF junction temperature TjOFF; wherein the gate-bias circuit comprises a gate-bias power supply PSVG and a first switching device M₁ con-nected to the gate-bias power supply PSVG; an end of the first switching device M₁ is connected to the gate-bias power supply PSVG, and another end of the first switching device M₁ is connected to a VG node; the VG node is connected to a gate of the DUT; the controlling circuit is configured to control the first switching device M₁ to connect the gate-bias power supply PSVG to the VG node to turn on the DUT when the system is operated in the measure mode; wherein the gate-bias circuit further comprises a third switching device M3; an end of the third switching device M₃ is connected to a ground GND, and another end of the third switching device M₃ is connected to the VG node; the third switching device M₃ is configured to receive a control signal VGOFF from the control-ling circuit to connect the ground GND to the VG node to turn off the DUT.
The system according to claim 1, wherein the TjON is given by TjON=Pstr×Rth(j-a)+Ta, where Ta is an ambient temperature and Rth(j-a) is a junction thermal resistance of the DUT at the ambient temperature Ta.
The system according to claim 1, wherein the OFF junction temperature TjOFF is given by TjOFF=Ta, where Ta is an ambient temperature.
The system according to claim 1, wherein the stressing circuit is further configured to: receive a first reference signal VdsCtrl and a second reference signal IdsCtrl from the controlling circuit; detect the signal VDIM from the drain terminal of the DUT and the signal VSIM from the source terminal of the DUT; control a voltage applied to the drain terminal of the DUT based on the received first reference signals VdsCtrl and the detected signal VDIM to regulate the drain-source voltage Vdsstr to be equal to VdsCtrl; and control a voltage applied to the VG node based on the received second reference signals IdsCtrl and the detected signal VSIM to regulate the drain-source cur-rent Idsstr to be equal to IdsCtrl. R₁
The system according to claim 1, further comprising a fourth diode D₄ having a cathode coupled to the drain terminal of the DUT, and configured for allowing the drain-source current Idsstr flowing only in one direction from the stressing circuit to the drain terminal of the DUT.
The system according to claim 1, further comprising a fifth diode D₅ having a cathode connected to the drain terminal of the DUT and configured for allowing the drain-source current Idsmea flowing only in one direction from the measure-bias circuit to the drain terminal of the DUT.
The system according to claim 1, wherein the cooling circuit comprises a fan configured to receive a control signal AirCtrl from the controlling circuit and generate a flow of air surrounding the DUT to cool down the DUT.
The system according to claim 1, further comprising 30 a man-machine interfacing unit configured for facilitating a user to select and set up operation modes and displaying operation setting menus and measurement results.
The system according to claim 1, further comprising a storage unit configured for storing operation setting param-eters and measurement results.
A method for measuring an intermittent operating life (IOL) of a GaN-based devices under test (DUT) having a source terminal, a drain terminal, and a gate terminal, the method comprising: stressing, by a stressing circuit, the DUT by applying a regulated stressing power Pstr to the DUT to increase a junction temperature of the DUT to an ON-junction temperature TjON; wherein the regulated stressing power Pstr is given by Pstr=Idsstr*Vdsstr, where Idsstr is a regulated drain-source current Idsstr passing through the DUT, and Vdsstr is a regulated drain-source voltage across the DUT; measuring, by a controlling circuit, a drain-source resistance Rds of the DUT and determining the drain-source resistance Rds to be an ON-drain-source resis-tance RdsON of the DUT when the junction tempera-ture of the DUT reaches the ON-junction temperature TjON; cooling, by a cooling circuit, the DUT to decrease the junction temperature of the DUT to an OFF junction temperature TjOFF; and measuring, by the controlling circuit, the drain-source resistance Rds of the DUT and determining the drain-source resistance Rds to be an OFF-drain-source resistance RdsOFF of the DUT when the junction temperature of the DUT reaches the OFF junction temperature TjOFF.
The method according to claim 14, wherein the TjON is given by TjON=Pstr×Rth(j-a)+Ta, where Ta is an ambient temperature and Rth(j-a) a junction thermal resistance of the DUT at the ambient temperature Ta.
The method according to claim 14, wherein the OFF-junction temperature TjOFF is given by TjOFF=Ta where Ta is an ambient temperature.
The method according to claim 14, wherein the step of stressing the DUT comprises: switching off, by the controlling circuit, a sixth switching device M₆ to block any current flowing from a mea-sure-bias circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a fourth switching device M₄ to allow a drain-source current Idsstr flow-ing from the stressing circuit to the drain terminal of the DUT; receiving, by the stressing circuit, a reference signal IdsCtrl from the controlling circuit; regulating, by the stressing unit circuit, the drain-source current Idsstr passing through the DUT based on the reference signal IdsCtrl; receiving, by the stressing circuit, a reference signal VdsCtrl from the controlling circuit; and regulating, by the stressing circuit, a drain-source voltage Vdsstr applied across the DUT based on the reference signal VdsCtrl.
The method according to claim 14, wherein the step of measuring the ON-drain-source resistance RdsON of the DUT comprises: switching off, by the controlling circuit, a fourth switch-ing device M₄ to block any current flowing from the stressing circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a sixth switching device M₆ to allow a drain-source current Idsmea flowing from a measure-bias circuit to the drain termi-nal of the DUT; switching on, by the controlling circuit, a first switching device M₁ to connect the gate terminal of the DUT to a power supply PSVG to turn on the DUT; receiving, by the measure-bias circuit, a reference signal IMCtrl from the controlling circuit; regulating, by the measure-bias circuit, the drain-source current Idsmea based on the received reference signal IMCtrl; receiving, by the controlling circuit, a signal VDIM from the drain terminal of the DUT and a signal VSIM from the source terminal of the DUT; and determining, by the controlling circuit, the ON-drain-source resistance RdsON of the DUT, wherein RdsON is given by R1×(VDIM-VSIM) RdsON =; VSIM where R₁ is a resistor connected between the source termi-nal of the DUT and a ground GND.
The method according to claim 14, wherein the step of cooling the DUT comprises: switching off, by the controlling circuit, a sixth switching device M₆ to block any current flowing from the measure-bias circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a third switching device M₃ to connect the gate terminal of the DUT to a ground GND to turn off the DUT; and turning on, by the controlling circuit, a fan to cool down the DUT for a preset period of time.
The method according to claim 14, wherein the step of measuring the OFF-drain-source resistance RdsOFF of the DUT comprises: 19 switching off, by the controlling circuit, a fourth switch-ing device M₄ to block any current flowing from the stressing circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a sixth switching device M₆ to allow a drain-source current Idsmea flowing from a measure-bias circuit to the drain termi-nal of the DUT; switching on, by the controlling circuit, a first switching device M₁ to connect the gate terminal of the DUT to a power supply PSVG to turn on the DUT; receiving, by the measure-bias circuit, a reference signal IMCtrl from the controlling circuit; regulating, by the measure-bias circuit, the drain-source current Idsmea based on the received reference signal IMCtrl; receiving, by the controlling circuit, a signal VDIM from the drain terminal of the DUT and a signal VSIM from the source terminal of the DUT; and determining, by the controlling circuit, the OFF-drain-source resistance RdsOFF of the DUT, wherein RdsOFF is given by R1×(VDIM-VSIM) RdsOFF =; VSIM where R₁ is a resistor connected between the source termi-nal of the DUT and a ground GND. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based device under test (DUT)
No layer stack recorded.
Materials described outside the worked examples.
GaN
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 14
Related documents with shared materials, methods, properties, or citations.
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Atlas literature
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US 12,038,469 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a circuit diagram of an intermittent oper- ating life (IOL) testing system and how it is connected to a GaN-based device under test (DUT) …
FIG. 2 depicts a circuit diagram of an intermittent oper- 15 ating life (IOL) testing system and how it is connected to a GaN-based device under test (DUT) …
FIG. 3 depicts a flowchart of a method for operating a testing system for measuring an intermittent operating life 20 (IOL) of a GaN-based device according to …
FIG. 4 depicts signal waveforms of operation of the testing system 10 according to some embodiments of the subject application. 25
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A system for measuring an intermittent operating life (IOL) of a GaN-based device under test (DUT), the system being operable in a stressing mode, a cooling mode, and a measure mode, the system being operable in the stressing mode, the measure mode, the cooling mode, and the measure mode in sequence, and comprising: 30 a controlling circuit configured for detecting a signal VDIM from a drain terminal of the DUT and a signal VSIM from a source terminal of the DUT and comput-ing a drain-source resistance Rds of the DUT when the system is operated in the measure mode; 35 a stressing circuit configured for applying a regulated stressing power Pstr to the DUT to increase a junction temperature of the DUT to an ON-junction temperature TjON when the system is operated in the stressing mode, wherein the regulated stressing power Pstr is given by Pstr=Idsstr*Vdsstr, where Idsstr is a regulated drain-source current passing through the DUT and Vdsstr is a regulated drain-source voltage Vdsstr across the DUT; a cooling circuit configured for, after the DUT is turned off, cooling the DUT to decrease the junction tempera-ture of the DUT to an OFF junction temperature TjOFF; a gate-bias circuit configured to receive a control signal VGM from the controlling circuit to turn on the DUT when the system is operated in the measure mode; and receive a control signal VGOFF from the controlling circuit to turn off the DUT when the system is operated in the cooling mode; and a measure-bias circuit configured to receive, after the DUT is turned on, a reference signal IMCtrl from the controlling circuit and supply a regulated drain-source current Idsmea to the DUT when the system is operated in the measure mode, such that the controlling circuit computes the drain-source resistance Rds of the DUT; wherein the controlling circuit is further configured to determine the drain-source resistance Rds to be an ON-drain-source resistance RdsON of the DUT if the drain-source resistance Rds is obtained when the junction temperature of the DUT reaches the ON-junction tem-perature TjON; and determine the drain-source resistance Rds to be an OFF-drain-source resistance RdsOFF of the DUT if the B₂ drain-source resistance Rds is obtained when the junc-tion temperature of the DUT reaches the OFF junction temperature TjOFF; wherein the gate-bias circuit comprises a gate-bias power supply PSVG and a first switching device M₁ con-nected to the gate-bias power supply PSVG; an end of the first switching device M₁ is connected to the gate-bias power supply PSVG, and another end of the first switching device M₁ is connected to a VG node; the VG node is connected to a gate of the DUT; the controlling circuit is configured to control the first switching device M₁ to connect the gate-bias power supply PSVG to the VG node to turn on the DUT when the system is operated in the measure mode; wherein the gate-bias circuit further comprises a third switching device M3; an end of the third switching device M₃ is connected to a ground GND, and another end of the third switching device M₃ is connected to the VG node; the third switching device M₃ is configured to receive a control signal VGOFF from the control-ling circuit to connect the ground GND to the VG node to turn off the DUT.
The system according to claim 1, wherein the TjON is given by TjON=Pstr×Rth(j-a)+Ta, where Ta is an ambient temperature and Rth(j-a) is a junction thermal resistance of the DUT at the ambient temperature Ta.
The system according to claim 1, wherein the OFF junction temperature TjOFF is given by TjOFF=Ta, where Ta is an ambient temperature.
The system according to claim 1, wherein the stressing circuit is further configured to: receive a first reference signal VdsCtrl and a second reference signal IdsCtrl from the controlling circuit; detect the signal VDIM from the drain terminal of the DUT and the signal VSIM from the source terminal of the DUT; control a voltage applied to the drain terminal of the DUT based on the received first reference signals VdsCtrl and the detected signal VDIM to regulate the drain-source voltage Vdsstr to be equal to VdsCtrl; and control a voltage applied to the VG node based on the received second reference signals IdsCtrl and the detected signal VSIM to regulate the drain-source cur-rent Idsstr to be equal to IdsCtrl. R₁
The system according to claim 1, further comprising a fourth diode D₄ having a cathode coupled to the drain terminal of the DUT, and configured for allowing the drain-source current Idsstr flowing only in one direction from the stressing circuit to the drain terminal of the DUT.
The system according to claim 1, further comprising a fifth diode D₅ having a cathode connected to the drain terminal of the DUT and configured for allowing the drain-source current Idsmea flowing only in one direction from the measure-bias circuit to the drain terminal of the DUT.
The system according to claim 1, wherein the cooling circuit comprises a fan configured to receive a control signal AirCtrl from the controlling circuit and generate a flow of air surrounding the DUT to cool down the DUT.
The system according to claim 1, further comprising 30 a man-machine interfacing unit configured for facilitating a user to select and set up operation modes and displaying operation setting menus and measurement results.
The system according to claim 1, further comprising a storage unit configured for storing operation setting param-eters and measurement results.
A method for measuring an intermittent operating life (IOL) of a GaN-based devices under test (DUT) having a source terminal, a drain terminal, and a gate terminal, the method comprising: stressing, by a stressing circuit, the DUT by applying a regulated stressing power Pstr to the DUT to increase a junction temperature of the DUT to an ON-junction temperature TjON; wherein the regulated stressing power Pstr is given by Pstr=Idsstr*Vdsstr, where Idsstr is a regulated drain-source current Idsstr passing through the DUT, and Vdsstr is a regulated drain-source voltage across the DUT; measuring, by a controlling circuit, a drain-source resistance Rds of the DUT and determining the drain-source resistance Rds to be an ON-drain-source resis-tance RdsON of the DUT when the junction tempera-ture of the DUT reaches the ON-junction temperature TjON; cooling, by a cooling circuit, the DUT to decrease the junction temperature of the DUT to an OFF junction temperature TjOFF; and measuring, by the controlling circuit, the drain-source resistance Rds of the DUT and determining the drain-source resistance Rds to be an OFF-drain-source resistance RdsOFF of the DUT when the junction temperature of the DUT reaches the OFF junction temperature TjOFF.
The method according to claim 14, wherein the TjON is given by TjON=Pstr×Rth(j-a)+Ta, where Ta is an ambient temperature and Rth(j-a) a junction thermal resistance of the DUT at the ambient temperature Ta.
The method according to claim 14, wherein the OFF-junction temperature TjOFF is given by TjOFF=Ta where Ta is an ambient temperature.
The method according to claim 14, wherein the step of stressing the DUT comprises: switching off, by the controlling circuit, a sixth switching device M₆ to block any current flowing from a mea-sure-bias circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a fourth switching device M₄ to allow a drain-source current Idsstr flow-ing from the stressing circuit to the drain terminal of the DUT; receiving, by the stressing circuit, a reference signal IdsCtrl from the controlling circuit; regulating, by the stressing unit circuit, the drain-source current Idsstr passing through the DUT based on the reference signal IdsCtrl; receiving, by the stressing circuit, a reference signal VdsCtrl from the controlling circuit; and regulating, by the stressing circuit, a drain-source voltage Vdsstr applied across the DUT based on the reference signal VdsCtrl.
The method according to claim 14, wherein the step of measuring the ON-drain-source resistance RdsON of the DUT comprises: switching off, by the controlling circuit, a fourth switch-ing device M₄ to block any current flowing from the stressing circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a sixth switching device M₆ to allow a drain-source current Idsmea flowing from a measure-bias circuit to the drain termi-nal of the DUT; switching on, by the controlling circuit, a first switching device M₁ to connect the gate terminal of the DUT to a power supply PSVG to turn on the DUT; receiving, by the measure-bias circuit, a reference signal IMCtrl from the controlling circuit; regulating, by the measure-bias circuit, the drain-source current Idsmea based on the received reference signal IMCtrl; receiving, by the controlling circuit, a signal VDIM from the drain terminal of the DUT and a signal VSIM from the source terminal of the DUT; and determining, by the controlling circuit, the ON-drain-source resistance RdsON of the DUT, wherein RdsON is given by R1×(VDIM-VSIM) RdsON =; VSIM where R₁ is a resistor connected between the source termi-nal of the DUT and a ground GND.
The method according to claim 14, wherein the step of cooling the DUT comprises: switching off, by the controlling circuit, a sixth switching device M₆ to block any current flowing from the measure-bias circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a third switching device M₃ to connect the gate terminal of the DUT to a ground GND to turn off the DUT; and turning on, by the controlling circuit, a fan to cool down the DUT for a preset period of time.
The method according to claim 14, wherein the step of measuring the OFF-drain-source resistance RdsOFF of the DUT comprises: 19 switching off, by the controlling circuit, a fourth switch-ing device M₄ to block any current flowing from the stressing circuit to the drain terminal of the DUT; switching on, by the controlling circuit, a sixth switching device M₆ to allow a drain-source current Idsmea flowing from a measure-bias circuit to the drain termi-nal of the DUT; switching on, by the controlling circuit, a first switching device M₁ to connect the gate terminal of the DUT to a power supply PSVG to turn on the DUT; receiving, by the measure-bias circuit, a reference signal IMCtrl from the controlling circuit; regulating, by the measure-bias circuit, the drain-source current Idsmea based on the received reference signal IMCtrl; receiving, by the controlling circuit, a signal VDIM from the drain terminal of the DUT and a signal VSIM from the source terminal of the DUT; and determining, by the controlling circuit, the OFF-drain-source resistance RdsOFF of the DUT, wherein RdsOFF is given by R1×(VDIM-VSIM) RdsOFF =; VSIM where R₁ is a resistor connected between the source termi-nal of the DUT and a ground GND. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based device under test (DUT)
No layer stack recorded.
Materials described outside the worked examples.
GaN
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 14
Related documents with shared materials, methods, properties, or citations.
Cited non-patent literature · 3
Cited non-patent literature · 3
Cited non-patent literature · 3
Cited non-patent literature · 3
