Patent
US 8,969,178METHOD OF MANUFACTURING LARGE AREA GALLIUM NITRIDE SUBSTRATE
Moon-sang LEE
US
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Patent
Atlas literature
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US 8,969,178Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 A through 1 D are cross-sectional views for describing a method of manufacturing a large area gallium nitride (GaN) substrate, according to an example …
FIG. 2 is a microscopic image showing cracks formed on an edge of a buffer layer on a silicon substrate; [0016]
FIG. 3 is a photo showing a surface of a GaN substrate grown according to an example embodiment; and [0017]
FIG. 4 is a photo showing a meltback formed on a rim of a silicon substrate when a GaN layer is grown without an insulation layer pattern.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
LISTING OF CLA IMS 1. A method of manufacturing a large area gallium nitride (GaN) substrate, the method comprising: forming a buffer layer on a silicon substrate; forming an insulation layer pattern on a rim of a top surface of the buffer layer; growing a GaN layer on the buffer layer, the GaN la y er including a single crystal G aN layer adjacent to a side surface of the insulation lay er pattern and a polyc rystalline GaN la v er on a top surface of the insulation layer pattern; and removing the insulation layer pattern, the p olycr y stalline GaN la y er on the t op surface of the insulation la y er pattern and corresponding portions of the buffer GaN layer and the silicon substrate under the insulation la y er p attern.
The method of claim 1, wherein the f o rming of the buffer layer includes using a metal organic chemical vapor deposition (MOCVD) method.
The method of claim 1, wherein the forming of the buffer layer includes forming at least one of a single layer of any one of aluminum nitride (A N), tantalum nitride (TaN), titanium nitride (TiN), hafnium nitride (H fN), G aN, and aluminum gallium nitride (A 1Ga N), and a triple layer of A I N, A I GaN, and G aN.
The method of claim 1, wherein the f o rming of the insulation layer pattern comprises: Page 2 Application No. 13/743,634 Attorney Docket No. 2557S I-00 1894-US forming a silicon oxide layer on the buffer layer; and patterning the silicon oxide layer.
The method of claim 1, wherein the fo rm ing of the insulation layer pattern includes forming one of silicon oxide, silicon nitride, alumina, and hafn ium oxide.
The method of claim 1, wherein the growing SVG 13743634.09-04-2014.HZTU₃SE₈PXXIFW1.CLM.1.svg 0.52 6.51 Black and white
The method of claim 1, wherein the forming of the insulation layer pattern includes forming the insulation layer pattern to a width of from about 0.5 mm to about 5 mm.
The method of claim 1, wherein the growing of the GaN layer includes using a hydride vapor phase epitaxy (HV PE) method.
The method of claim 1, further comprising: removing the silicon substrate.
Layer stacks claimed or described, ordered top of device to substrate.
large area GaN substrate
Materials described outside the worked examples.
gallium nitride (GaN) substrate
GaN
silicon substrate
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
silicon substrate diameter | 6–18 inches | Si |
silicon substrate thickness | 100–1000 μm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,969,178Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 A through 1 D are cross-sectional views for describing a method of manufacturing a large area gallium nitride (GaN) substrate, according to an example …
FIG. 2 is a microscopic image showing cracks formed on an edge of a buffer layer on a silicon substrate; [0016]
FIG. 3 is a photo showing a surface of a GaN substrate grown according to an example embodiment; and [0017]
FIG. 4 is a photo showing a meltback formed on a rim of a silicon substrate when a GaN layer is grown without an insulation layer pattern.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
LISTING OF CLA IMS 1. A method of manufacturing a large area gallium nitride (GaN) substrate, the method comprising: forming a buffer layer on a silicon substrate; forming an insulation layer pattern on a rim of a top surface of the buffer layer; growing a GaN layer on the buffer layer, the GaN la y er including a single crystal G aN layer adjacent to a side surface of the insulation lay er pattern and a polyc rystalline GaN la v er on a top surface of the insulation layer pattern; and removing the insulation layer pattern, the p olycr y stalline GaN la y er on the t op surface of the insulation la y er pattern and corresponding portions of the buffer GaN layer and the silicon substrate under the insulation la y er p attern.
The method of claim 1, wherein the f o rming of the buffer layer includes using a metal organic chemical vapor deposition (MOCVD) method.
The method of claim 1, wherein the forming of the buffer layer includes forming at least one of a single layer of any one of aluminum nitride (A N), tantalum nitride (TaN), titanium nitride (TiN), hafnium nitride (H fN), G aN, and aluminum gallium nitride (A 1Ga N), and a triple layer of A I N, A I GaN, and G aN.
The method of claim 1, wherein the f o rming of the insulation layer pattern comprises: Page 2 Application No. 13/743,634 Attorney Docket No. 2557S I-00 1894-US forming a silicon oxide layer on the buffer layer; and patterning the silicon oxide layer.
The method of claim 1, wherein the fo rm ing of the insulation layer pattern includes forming one of silicon oxide, silicon nitride, alumina, and hafn ium oxide.
The method of claim 1, wherein the growing SVG 13743634.09-04-2014.HZTU₃SE₈PXXIFW1.CLM.1.svg 0.52 6.51 Black and white
The method of claim 1, wherein the forming of the insulation layer pattern includes forming the insulation layer pattern to a width of from about 0.5 mm to about 5 mm.
The method of claim 1, wherein the growing of the GaN layer includes using a hydride vapor phase epitaxy (HV PE) method.
The method of claim 1, further comprising: removing the silicon substrate.
Layer stacks claimed or described, ordered top of device to substrate.
large area GaN substrate
Materials described outside the worked examples.
gallium nitride (GaN) substrate
GaN
silicon substrate
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
silicon substrate diameter | 6–18 inches | Si |
silicon substrate thickness | 100–1000 μm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,969,178Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 A through 1 D are cross-sectional views for describing a method of manufacturing a large area gallium nitride (GaN) substrate, according to an example …
FIG. 2 is a microscopic image showing cracks formed on an edge of a buffer layer on a silicon substrate; [0016]
FIG. 3 is a photo showing a surface of a GaN substrate grown according to an example embodiment; and [0017]
FIG. 4 is a photo showing a meltback formed on a rim of a silicon substrate when a GaN layer is grown without an insulation layer pattern.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
LISTING OF CLA IMS 1. A method of manufacturing a large area gallium nitride (GaN) substrate, the method comprising: forming a buffer layer on a silicon substrate; forming an insulation layer pattern on a rim of a top surface of the buffer layer; growing a GaN layer on the buffer layer, the GaN la y er including a single crystal G aN layer adjacent to a side surface of the insulation lay er pattern and a polyc rystalline GaN la v er on a top surface of the insulation layer pattern; and removing the insulation layer pattern, the p olycr y stalline GaN la y er on the t op surface of the insulation la y er pattern and corresponding portions of the buffer GaN layer and the silicon substrate under the insulation la y er p attern.
The method of claim 1, wherein the f o rming of the buffer layer includes using a metal organic chemical vapor deposition (MOCVD) method.
The method of claim 1, wherein the forming of the buffer layer includes forming at least one of a single layer of any one of aluminum nitride (A N), tantalum nitride (TaN), titanium nitride (TiN), hafnium nitride (H fN), G aN, and aluminum gallium nitride (A 1Ga N), and a triple layer of A I N, A I GaN, and G aN.
The method of claim 1, wherein the f o rming of the insulation layer pattern comprises: Page 2 Application No. 13/743,634 Attorney Docket No. 2557S I-00 1894-US forming a silicon oxide layer on the buffer layer; and patterning the silicon oxide layer.
The method of claim 1, wherein the fo rm ing of the insulation layer pattern includes forming one of silicon oxide, silicon nitride, alumina, and hafn ium oxide.
The method of claim 1, wherein the growing SVG 13743634.09-04-2014.HZTU₃SE₈PXXIFW1.CLM.1.svg 0.52 6.51 Black and white
The method of claim 1, wherein the forming of the insulation layer pattern includes forming the insulation layer pattern to a width of from about 0.5 mm to about 5 mm.
The method of claim 1, wherein the growing of the GaN layer includes using a hydride vapor phase epitaxy (HV PE) method.
The method of claim 1, further comprising: removing the silicon substrate.
Layer stacks claimed or described, ordered top of device to substrate.
large area GaN substrate
Materials described outside the worked examples.
gallium nitride (GaN) substrate
GaN
silicon substrate
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
silicon substrate diameter | 6–18 inches | Si |
silicon substrate thickness | 100–1000 μm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,969,178Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 A through 1 D are cross-sectional views for describing a method of manufacturing a large area gallium nitride (GaN) substrate, according to an example …
FIG. 2 is a microscopic image showing cracks formed on an edge of a buffer layer on a silicon substrate; [0016]
FIG. 3 is a photo showing a surface of a GaN substrate grown according to an example embodiment; and [0017]
FIG. 4 is a photo showing a meltback formed on a rim of a silicon substrate when a GaN layer is grown without an insulation layer pattern.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
LISTING OF CLA IMS 1. A method of manufacturing a large area gallium nitride (GaN) substrate, the method comprising: forming a buffer layer on a silicon substrate; forming an insulation layer pattern on a rim of a top surface of the buffer layer; growing a GaN layer on the buffer layer, the GaN la y er including a single crystal G aN layer adjacent to a side surface of the insulation lay er pattern and a polyc rystalline GaN la v er on a top surface of the insulation layer pattern; and removing the insulation layer pattern, the p olycr y stalline GaN la y er on the t op surface of the insulation la y er pattern and corresponding portions of the buffer GaN layer and the silicon substrate under the insulation la y er p attern.
The method of claim 1, wherein the f o rming of the buffer layer includes using a metal organic chemical vapor deposition (MOCVD) method.
The method of claim 1, wherein the forming of the buffer layer includes forming at least one of a single layer of any one of aluminum nitride (A N), tantalum nitride (TaN), titanium nitride (TiN), hafnium nitride (H fN), G aN, and aluminum gallium nitride (A 1Ga N), and a triple layer of A I N, A I GaN, and G aN.
The method of claim 1, wherein the f o rming of the insulation layer pattern comprises: Page 2 Application No. 13/743,634 Attorney Docket No. 2557S I-00 1894-US forming a silicon oxide layer on the buffer layer; and patterning the silicon oxide layer.
The method of claim 1, wherein the fo rm ing of the insulation layer pattern includes forming one of silicon oxide, silicon nitride, alumina, and hafn ium oxide.
The method of claim 1, wherein the growing SVG 13743634.09-04-2014.HZTU₃SE₈PXXIFW1.CLM.1.svg 0.52 6.51 Black and white
The method of claim 1, wherein the forming of the insulation layer pattern includes forming the insulation layer pattern to a width of from about 0.5 mm to about 5 mm.
The method of claim 1, wherein the growing of the GaN layer includes using a hydride vapor phase epitaxy (HV PE) method.
The method of claim 1, further comprising: removing the silicon substrate.
Layer stacks claimed or described, ordered top of device to substrate.
large area GaN substrate
Materials described outside the worked examples.
gallium nitride (GaN) substrate
GaN
silicon substrate
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
silicon substrate diameter | 6–18 inches | Si |
silicon substrate thickness | 100–1000 μm |
Related documents with shared materials, methods, properties, or citations.
buffer layer
aluminum nitride
AlN
tantalum nitride
TaN
titanium nitride
TiN
hafnium nitride
HfN
aluminum gallium nitride
AlGaN
silicon oxide
SiO₂
silicon nitride
Si₃N₄
alumina
Al₂O₃
hafnium oxide
HfO₂
buffer layer thickness | 5–50000 nm | buffer layer |
insulation layer pattern width | 0.5–5 mm | SiO₂ |
insulation layer pattern thickness | 5–2000 μm | SiO₂ |
buffer layer
aluminum nitride
AlN
tantalum nitride
TaN
titanium nitride
TiN
hafnium nitride
HfN
aluminum gallium nitride
AlGaN
silicon oxide
SiO₂
silicon nitride
Si₃N₄
alumina
Al₂O₃
hafnium oxide
HfO₂
buffer layer thickness | 5–50000 nm | buffer layer |
insulation layer pattern width | 0.5–5 mm | SiO₂ |
insulation layer pattern thickness | 5–2000 μm | SiO₂ |
buffer layer
aluminum nitride
AlN
tantalum nitride
TaN
titanium nitride
TiN
hafnium nitride
HfN
aluminum gallium nitride
AlGaN
silicon oxide
SiO₂
silicon nitride
Si₃N₄
alumina
Al₂O₃
hafnium oxide
HfO₂
buffer layer thickness | 5–50000 nm | buffer layer |
insulation layer pattern width | 0.5–5 mm | SiO₂ |
insulation layer pattern thickness | 5–2000 μm | SiO₂ |
buffer layer
aluminum nitride
AlN
tantalum nitride
TaN
titanium nitride
TiN
hafnium nitride
HfN
aluminum gallium nitride
AlGaN
silicon oxide
SiO₂
silicon nitride
Si₃N₄
alumina
Al₂O₃
hafnium oxide
HfO₂
buffer layer thickness | 5–50000 nm | buffer layer |
insulation layer pattern width | 0.5–5 mm | SiO₂ |
insulation layer pattern thickness | 5–2000 μm | SiO₂ |