Patent
US 9,917,171LOW-RESISTIVE, CMOS-COMPATIBLE, AU-FREE OHMIC CONTACT TO N-INP
Utz Herwig Hahn
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,917,171Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-9 are 2D cross-sectional views illustrating the fabrication of a device, according to embodiments.
FIG. 2. Then, the n-doped InP layer 1 and the p-doped InP layer 3 may be covered with a cladding material 4, step S 40,
FIG. 3. Finally, one may open vias or trenches 5, 5 a in the cladding material on each side of the stack 2, step S₅ 0, see also
FIG. 4. The stacks 6, 6a of alternating layers can subsequently be grown in respective vias 5, 5 a, step S 60, see
FIG. 5. The total layer thickness is of about 75 nm. The ratio Ni to Si is approximately 1: 1 and the lower layers 61, 62, 61a, 62a are very thin, i.e., …
FIG. 6. A preferred temperature for this first step is 240C. The second annealing is performed at a higher temperature (up to 450C), so as for the upper layers …
FIG. 7. During the second annealing step, the lower regions 7, 7a (low-resistive compounds of
FIGS. 9 and 10, an aspect of the invention is first described, which concerns a device 10 that may for instance be an electronic device or an opto-electronic …
FIG. 10 shows a 3D view of the device of
FIG. 11, which notably depicts a sectional view of the epitaxial layer stack of I II-V semiconductor material layers 22-24. The gain stack 2 may notably …
FIG. 12, another aspect of the invention is described, which concerns a method of fabrication of a device 10 such as described above. Essentially, this method …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: an n-doped InP layer; and an ohmic contact, in contact with the n-doped I nP layer, wherein [[said]]the ohmic contact comp ri ses an annealed stack of at least a first layer of Ni on top of and in contact with the n-doped InP layer, a second layer of Si on top of and in contact with the first layer, a third layer of Ni on top of and in contact with the second layer, and a fourth layer of Si on top of and in contact with the third layer, wherein the first layer and the second layer have, each, an average thickness that is substantially less than 1/5 an average thickness of each of the third layer and the fourth layer; the n-doped I nP layer and one of the layers of the stack in contact therewith are at least partly intermixed; and any two adjacent layers of the stack are at least partly intermixed. Currently amended
The device according to claim 1, comprising two ohmic contacts, each according to [[said]]the ohmic contact, whereby each of the two ohmic contacts is in contact with the n-doped I nP layer. Currently amended
Canceled
Canceled
Canceled
Canceled
The device according to claim [[5]] 1, wherein the first layer and the second layer have, each, an average thickness that is equal to or less than 1/8 of the average thickness of the third layer and the fourth layer. Currently amended
The device according to claim [[4]] 1, wherein the ratio of Ni to Si in the annealed stack is substantially of 1:1. Currently amended
The device according to claim 7, wherein a specific contact resistivity of [[said]]the ohmic contact is less than 10-7 Q.cm 2. Currently amended
The device according to claim 7, wherein a specific contact resistivity of [[said]]the ohmic contact is less than 10-8 Q.cm 2. Currently amended
The device according to claim [[7]] !, wherein a height of [[said]]the stack is less than 80nm as measured along a stacking direction thereof. Currently amended
The device according to claim 8, wherein: a thickness of each of [[said]]the first layer of Ni and the second layer of Si is 3 nm; a thickness of [[said]]the third layer of Ni is 25nm; and a thickness of [[said]]the fourth layer of Si is 25nm, as measured along [[said]]the stacking direction. Currently amended
The device according to claim [[2]] 1, wherein a specific contact resistivity of [[said]]the ohmic contact is less than 10-6 Q.cm 2. Currently amended
A method of fabrication of a device comprising an n-doped InP layer and an ohmic contact, in contact with the n-doped I nP layer, [[said]]the method comprising: providing [[said]]the n-doped I nP layer; growing a stack of at least, a first layer of Ni on top of and in contact with the n-doped InP layer, a second layer of Si on top of and in contact with the first layer, a third layer of Ni on top of and in contact with the second layer, and a fourth layer of Si on top of and in contact with the third layer, wherein the first layer and the second layer have, each, an average thickness that is substantially less than 1/5 an average thickness of each of the third layer and the fourth layer; and annealing the device such that: the n-doped I nP layer and one of the layers of the stack in contact therewith are at least partly intermixed; and any two adjacent layers of the stack are at least partly intermixed; wherein [[said]]the ohmic contact comprises [[said]]the annealed stack. Currently amended
The method according to claim 17, wherein:, annealing comprises: annealing the device at a first temperature that is between 220C and 300 C, so as for [[said]]the one of the four layers in contact with the n-doped I nP layer to react therewith and form a region comprising a Ni I nP compound; and annealing the device at a second temperature that is higher than [[said]]the first temperature and lower than or equal to 450C, such that any two adjacent layers of the stack are at least partly intermixed. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
Au-free ohmic contact device on n-InP
Optoelectronic/photonic device with active gain stack and ohmic contacts
Materials described outside the worked examples.
n-doped InP
InP
Nickel
Ni
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5. The total layer thickness is of about 75 nm. The ratio Ni to Si is approximately 1: 1 and the lower layers 61, 62, 61a, 62a are very thin, i.e., …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
specific contact resistivity upper bound (claim 12) | — | — |
specific contact resistivity upper bound (claim 10) | — | — |
specific contact resistivity upper bound (claim 11) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,917,171Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-9 are 2D cross-sectional views illustrating the fabrication of a device, according to embodiments.
FIG. 2. Then, the n-doped InP layer 1 and the p-doped InP layer 3 may be covered with a cladding material 4, step S 40,
FIG. 3. Finally, one may open vias or trenches 5, 5 a in the cladding material on each side of the stack 2, step S₅ 0, see also
FIG. 4. The stacks 6, 6a of alternating layers can subsequently be grown in respective vias 5, 5 a, step S 60, see
FIG. 5. The total layer thickness is of about 75 nm. The ratio Ni to Si is approximately 1: 1 and the lower layers 61, 62, 61a, 62a are very thin, i.e., …
FIG. 6. A preferred temperature for this first step is 240C. The second annealing is performed at a higher temperature (up to 450C), so as for the upper layers …
FIG. 7. During the second annealing step, the lower regions 7, 7a (low-resistive compounds of
FIGS. 9 and 10, an aspect of the invention is first described, which concerns a device 10 that may for instance be an electronic device or an opto-electronic …
FIG. 10 shows a 3D view of the device of
FIG. 11, which notably depicts a sectional view of the epitaxial layer stack of I II-V semiconductor material layers 22-24. The gain stack 2 may notably …
FIG. 12, another aspect of the invention is described, which concerns a method of fabrication of a device 10 such as described above. Essentially, this method …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: an n-doped InP layer; and an ohmic contact, in contact with the n-doped I nP layer, wherein [[said]]the ohmic contact comp ri ses an annealed stack of at least a first layer of Ni on top of and in contact with the n-doped InP layer, a second layer of Si on top of and in contact with the first layer, a third layer of Ni on top of and in contact with the second layer, and a fourth layer of Si on top of and in contact with the third layer, wherein the first layer and the second layer have, each, an average thickness that is substantially less than 1/5 an average thickness of each of the third layer and the fourth layer; the n-doped I nP layer and one of the layers of the stack in contact therewith are at least partly intermixed; and any two adjacent layers of the stack are at least partly intermixed. Currently amended
The device according to claim 1, comprising two ohmic contacts, each according to [[said]]the ohmic contact, whereby each of the two ohmic contacts is in contact with the n-doped I nP layer. Currently amended
Canceled
Canceled
Canceled
Canceled
The device according to claim [[5]] 1, wherein the first layer and the second layer have, each, an average thickness that is equal to or less than 1/8 of the average thickness of the third layer and the fourth layer. Currently amended
The device according to claim [[4]] 1, wherein the ratio of Ni to Si in the annealed stack is substantially of 1:1. Currently amended
The device according to claim 7, wherein a specific contact resistivity of [[said]]the ohmic contact is less than 10-7 Q.cm 2. Currently amended
The device according to claim 7, wherein a specific contact resistivity of [[said]]the ohmic contact is less than 10-8 Q.cm 2. Currently amended
The device according to claim [[7]] !, wherein a height of [[said]]the stack is less than 80nm as measured along a stacking direction thereof. Currently amended
The device according to claim 8, wherein: a thickness of each of [[said]]the first layer of Ni and the second layer of Si is 3 nm; a thickness of [[said]]the third layer of Ni is 25nm; and a thickness of [[said]]the fourth layer of Si is 25nm, as measured along [[said]]the stacking direction. Currently amended
The device according to claim [[2]] 1, wherein a specific contact resistivity of [[said]]the ohmic contact is less than 10-6 Q.cm 2. Currently amended
A method of fabrication of a device comprising an n-doped InP layer and an ohmic contact, in contact with the n-doped I nP layer, [[said]]the method comprising: providing [[said]]the n-doped I nP layer; growing a stack of at least, a first layer of Ni on top of and in contact with the n-doped InP layer, a second layer of Si on top of and in contact with the first layer, a third layer of Ni on top of and in contact with the second layer, and a fourth layer of Si on top of and in contact with the third layer, wherein the first layer and the second layer have, each, an average thickness that is substantially less than 1/5 an average thickness of each of the third layer and the fourth layer; and annealing the device such that: the n-doped I nP layer and one of the layers of the stack in contact therewith are at least partly intermixed; and any two adjacent layers of the stack are at least partly intermixed; wherein [[said]]the ohmic contact comprises [[said]]the annealed stack. Currently amended
The method according to claim 17, wherein:, annealing comprises: annealing the device at a first temperature that is between 220C and 300 C, so as for [[said]]the one of the four layers in contact with the n-doped I nP layer to react therewith and form a region comprising a Ni I nP compound; and annealing the device at a second temperature that is higher than [[said]]the first temperature and lower than or equal to 450C, such that any two adjacent layers of the stack are at least partly intermixed. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
Au-free ohmic contact device on n-InP
Optoelectronic/photonic device with active gain stack and ohmic contacts
Materials described outside the worked examples.
n-doped InP
InP
Nickel
Ni
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5. The total layer thickness is of about 75 nm. The ratio Ni to Si is approximately 1: 1 and the lower layers 61, 62, 61a, 62a are very thin, i.e., …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
specific contact resistivity upper bound (claim 12) | — | — |
specific contact resistivity upper bound (claim 10) | — | — |
specific contact resistivity upper bound (claim 11) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,917,171Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-9 are 2D cross-sectional views illustrating the fabrication of a device, according to embodiments.
FIG. 2. Then, the n-doped InP layer 1 and the p-doped InP layer 3 may be covered with a cladding material 4, step S 40,
FIG. 3. Finally, one may open vias or trenches 5, 5 a in the cladding material on each side of the stack 2, step S₅ 0, see also
FIG. 4. The stacks 6, 6a of alternating layers can subsequently be grown in respective vias 5, 5 a, step S 60, see
FIG. 5. The total layer thickness is of about 75 nm. The ratio Ni to Si is approximately 1: 1 and the lower layers 61, 62, 61a, 62a are very thin, i.e., …
FIG. 6. A preferred temperature for this first step is 240C. The second annealing is performed at a higher temperature (up to 450C), so as for the upper layers …
FIG. 7. During the second annealing step, the lower regions 7, 7a (low-resistive compounds of
FIGS. 9 and 10, an aspect of the invention is first described, which concerns a device 10 that may for instance be an electronic device or an opto-electronic …
FIG. 10 shows a 3D view of the device of
FIG. 11, which notably depicts a sectional view of the epitaxial layer stack of I II-V semiconductor material layers 22-24. The gain stack 2 may notably …
FIG. 12, another aspect of the invention is described, which concerns a method of fabrication of a device 10 such as described above. Essentially, this method …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: an n-doped InP layer; and an ohmic contact, in contact with the n-doped I nP layer, wherein [[said]]the ohmic contact comp ri ses an annealed stack of at least a first layer of Ni on top of and in contact with the n-doped InP layer, a second layer of Si on top of and in contact with the first layer, a third layer of Ni on top of and in contact with the second layer, and a fourth layer of Si on top of and in contact with the third layer, wherein the first layer and the second layer have, each, an average thickness that is substantially less than 1/5 an average thickness of each of the third layer and the fourth layer; the n-doped I nP layer and one of the layers of the stack in contact therewith are at least partly intermixed; and any two adjacent layers of the stack are at least partly intermixed. Currently amended
The device according to claim 1, comprising two ohmic contacts, each according to [[said]]the ohmic contact, whereby each of the two ohmic contacts is in contact with the n-doped I nP layer. Currently amended
Canceled
Canceled
Canceled
Canceled
The device according to claim [[5]] 1, wherein the first layer and the second layer have, each, an average thickness that is equal to or less than 1/8 of the average thickness of the third layer and the fourth layer. Currently amended
The device according to claim [[4]] 1, wherein the ratio of Ni to Si in the annealed stack is substantially of 1:1. Currently amended
The device according to claim 7, wherein a specific contact resistivity of [[said]]the ohmic contact is less than 10-7 Q.cm 2. Currently amended
The device according to claim 7, wherein a specific contact resistivity of [[said]]the ohmic contact is less than 10-8 Q.cm 2. Currently amended
The device according to claim [[7]] !, wherein a height of [[said]]the stack is less than 80nm as measured along a stacking direction thereof. Currently amended
The device according to claim 8, wherein: a thickness of each of [[said]]the first layer of Ni and the second layer of Si is 3 nm; a thickness of [[said]]the third layer of Ni is 25nm; and a thickness of [[said]]the fourth layer of Si is 25nm, as measured along [[said]]the stacking direction. Currently amended
The device according to claim [[2]] 1, wherein a specific contact resistivity of [[said]]the ohmic contact is less than 10-6 Q.cm 2. Currently amended
A method of fabrication of a device comprising an n-doped InP layer and an ohmic contact, in contact with the n-doped I nP layer, [[said]]the method comprising: providing [[said]]the n-doped I nP layer; growing a stack of at least, a first layer of Ni on top of and in contact with the n-doped InP layer, a second layer of Si on top of and in contact with the first layer, a third layer of Ni on top of and in contact with the second layer, and a fourth layer of Si on top of and in contact with the third layer, wherein the first layer and the second layer have, each, an average thickness that is substantially less than 1/5 an average thickness of each of the third layer and the fourth layer; and annealing the device such that: the n-doped I nP layer and one of the layers of the stack in contact therewith are at least partly intermixed; and any two adjacent layers of the stack are at least partly intermixed; wherein [[said]]the ohmic contact comprises [[said]]the annealed stack. Currently amended
The method according to claim 17, wherein:, annealing comprises: annealing the device at a first temperature that is between 220C and 300 C, so as for [[said]]the one of the four layers in contact with the n-doped I nP layer to react therewith and form a region comprising a Ni I nP compound; and annealing the device at a second temperature that is higher than [[said]]the first temperature and lower than or equal to 450C, such that any two adjacent layers of the stack are at least partly intermixed. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
Au-free ohmic contact device on n-InP
Optoelectronic/photonic device with active gain stack and ohmic contacts
Materials described outside the worked examples.
n-doped InP
InP
Nickel
Ni
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5. The total layer thickness is of about 75 nm. The ratio Ni to Si is approximately 1: 1 and the lower layers 61, 62, 61a, 62a are very thin, i.e., …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
specific contact resistivity upper bound (claim 12) | — | — |
specific contact resistivity upper bound (claim 10) | — | — |
specific contact resistivity upper bound (claim 11) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,917,171Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-9 are 2D cross-sectional views illustrating the fabrication of a device, according to embodiments.
FIG. 2. Then, the n-doped InP layer 1 and the p-doped InP layer 3 may be covered with a cladding material 4, step S 40,
FIG. 3. Finally, one may open vias or trenches 5, 5 a in the cladding material on each side of the stack 2, step S₅ 0, see also
FIG. 4. The stacks 6, 6a of alternating layers can subsequently be grown in respective vias 5, 5 a, step S 60, see
FIG. 5. The total layer thickness is of about 75 nm. The ratio Ni to Si is approximately 1: 1 and the lower layers 61, 62, 61a, 62a are very thin, i.e., …
FIG. 6. A preferred temperature for this first step is 240C. The second annealing is performed at a higher temperature (up to 450C), so as for the upper layers …
FIG. 7. During the second annealing step, the lower regions 7, 7a (low-resistive compounds of
FIGS. 9 and 10, an aspect of the invention is first described, which concerns a device 10 that may for instance be an electronic device or an opto-electronic …
FIG. 10 shows a 3D view of the device of
FIG. 11, which notably depicts a sectional view of the epitaxial layer stack of I II-V semiconductor material layers 22-24. The gain stack 2 may notably …
FIG. 12, another aspect of the invention is described, which concerns a method of fabrication of a device 10 such as described above. Essentially, this method …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: an n-doped InP layer; and an ohmic contact, in contact with the n-doped I nP layer, wherein [[said]]the ohmic contact comp ri ses an annealed stack of at least a first layer of Ni on top of and in contact with the n-doped InP layer, a second layer of Si on top of and in contact with the first layer, a third layer of Ni on top of and in contact with the second layer, and a fourth layer of Si on top of and in contact with the third layer, wherein the first layer and the second layer have, each, an average thickness that is substantially less than 1/5 an average thickness of each of the third layer and the fourth layer; the n-doped I nP layer and one of the layers of the stack in contact therewith are at least partly intermixed; and any two adjacent layers of the stack are at least partly intermixed. Currently amended
The device according to claim 1, comprising two ohmic contacts, each according to [[said]]the ohmic contact, whereby each of the two ohmic contacts is in contact with the n-doped I nP layer. Currently amended
Canceled
Canceled
Canceled
Canceled
The device according to claim [[5]] 1, wherein the first layer and the second layer have, each, an average thickness that is equal to or less than 1/8 of the average thickness of the third layer and the fourth layer. Currently amended
The device according to claim [[4]] 1, wherein the ratio of Ni to Si in the annealed stack is substantially of 1:1. Currently amended
The device according to claim 7, wherein a specific contact resistivity of [[said]]the ohmic contact is less than 10-7 Q.cm 2. Currently amended
The device according to claim 7, wherein a specific contact resistivity of [[said]]the ohmic contact is less than 10-8 Q.cm 2. Currently amended
The device according to claim [[7]] !, wherein a height of [[said]]the stack is less than 80nm as measured along a stacking direction thereof. Currently amended
The device according to claim 8, wherein: a thickness of each of [[said]]the first layer of Ni and the second layer of Si is 3 nm; a thickness of [[said]]the third layer of Ni is 25nm; and a thickness of [[said]]the fourth layer of Si is 25nm, as measured along [[said]]the stacking direction. Currently amended
The device according to claim [[2]] 1, wherein a specific contact resistivity of [[said]]the ohmic contact is less than 10-6 Q.cm 2. Currently amended
A method of fabrication of a device comprising an n-doped InP layer and an ohmic contact, in contact with the n-doped I nP layer, [[said]]the method comprising: providing [[said]]the n-doped I nP layer; growing a stack of at least, a first layer of Ni on top of and in contact with the n-doped InP layer, a second layer of Si on top of and in contact with the first layer, a third layer of Ni on top of and in contact with the second layer, and a fourth layer of Si on top of and in contact with the third layer, wherein the first layer and the second layer have, each, an average thickness that is substantially less than 1/5 an average thickness of each of the third layer and the fourth layer; and annealing the device such that: the n-doped I nP layer and one of the layers of the stack in contact therewith are at least partly intermixed; and any two adjacent layers of the stack are at least partly intermixed; wherein [[said]]the ohmic contact comprises [[said]]the annealed stack. Currently amended
The method according to claim 17, wherein:, annealing comprises: annealing the device at a first temperature that is between 220C and 300 C, so as for [[said]]the one of the four layers in contact with the n-doped I nP layer to react therewith and form a region comprising a Ni I nP compound; and annealing the device at a second temperature that is higher than [[said]]the first temperature and lower than or equal to 450C, such that any two adjacent layers of the stack are at least partly intermixed. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
Au-free ohmic contact device on n-InP
Optoelectronic/photonic device with active gain stack and ohmic contacts
Materials described outside the worked examples.
n-doped InP
InP
Nickel
Ni
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5. The total layer thickness is of about 75 nm. The ratio Ni to Si is approximately 1: 1 and the lower layers 61, 62, 61a, 62a are very thin, i.e., …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
specific contact resistivity upper bound (claim 12) | — | — |
specific contact resistivity upper bound (claim 10) | — | — |
specific contact resistivity upper bound (claim 11) |
Related documents with shared materials, methods, properties, or citations.
Silicon
Si
III-V semiconductor material layers (active gain stack)
NiInP compound
FIG. 11, which notably depicts a sectional view of the epitaxial layer stack of I II-V semiconductor material layers 22-24. The gain stack 2 may notably …
| — |
| — |
typical specific contact resistivity described in embodiment | 1e-8 Ω·cm² | — |
Thickness | ≤ 80 nm | — |
Silicon
Si
III-V semiconductor material layers (active gain stack)
NiInP compound
FIG. 11, which notably depicts a sectional view of the epitaxial layer stack of I II-V semiconductor material layers 22-24. The gain stack 2 may notably …
| — |
| — |
typical specific contact resistivity described in embodiment | 1e-8 Ω·cm² | — |
Thickness | ≤ 80 nm | — |
Silicon
Si
III-V semiconductor material layers (active gain stack)
NiInP compound
FIG. 11, which notably depicts a sectional view of the epitaxial layer stack of I II-V semiconductor material layers 22-24. The gain stack 2 may notably …
| — |
| — |
typical specific contact resistivity described in embodiment | 1e-8 Ω·cm² | — |
Thickness | ≤ 80 nm | — |
Silicon
Si
III-V semiconductor material layers (active gain stack)
NiInP compound
FIG. 11, which notably depicts a sectional view of the epitaxial layer stack of I II-V semiconductor material layers 22-24. The gain stack 2 may notably …
| — |
| — |
typical specific contact resistivity described in embodiment | 1e-8 Ω·cm² | — |
Thickness | ≤ 80 nm | — |