Patent
US 11,322,910INDIUM-PHOSPHIDE VCSEL WITH DIELECTRIC DBR
Jae Y. Park
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,322,910Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An optoelectronic device, comprising: a carrier substrate; a lower distributed Bragg-reflector (DBR) stack disposed on an area of the substrate and comprising alternating first dielectric and semiconductor layers; a set of epitaxial layers disposed over the lower DBR, wherein the set of epitaxial layers comprises one or more III -V semiconductor materials and defines: a quantum well structure; and a confinement layer; an upper DBR stack disposed over the set of epitaxial layers and comprising alternating second dielectric and semiconductor layers; electrodes coupled to apply an excitation current to the quantum well structure, wherein at least one of the electrodes comprises a metal ring disposed at an inner side of at least one of the DBR stacks in proximity to the quantum well structure; and one or more metal vias passing through the at least one of the DBR stacks so as to connect the metal ring at the inner side of the at least one of the DBR stacks to an electrical contact on an outer side of the at least one of the DBR stacks. Currently amended
The optoelectronic device according to claim 1, wherein the carrier substrate comprises a silicon (Si) wafer. Original
The optoelectronic device according to claim 1, wherein the alternating first dielectric and semiconductor layers comprise alternating layers of silicon dioxide (SiO 2) and amorphous silicon (a-Si). Original
The optoelectronic device according to claim 1, wherein the alternating first dielectric and semiconductor layers comprise alternating layers of aluminum nitride (AlN) and a-Si. Original
The optoelectronic device according to claim 1, wherein the one or more I II-V semiconductor materials are selected from a group of materials consisting of indium phosphide (InP), indium-gallium-arsenide (InGaAs), indium-gallium-arsenide- phosphide (InGaAsP), aluminum-gallium-indium-arsenide (AlGaInAs) and aluminum-gallium-arsenide-antimonide (AlGaAsSb).
The optoelectronic device according to claim 1, wherein the confinement layer comprises: a central part comprising a I II -V semiconductor material; and a peripheral part surrounding the central part and comprising a dielectric material. Original
The optoelectronic device according to claim 1, wherein the confinement layer comprises a buried tunnel junction. Original
The optoelectronic device according to claim 1, wherein the second dielectric and semiconductor layers comprise alternating layers of SiO 2 and amorphous silicon. Original
The optoelectronic device according to claim 1, wherein the electrodes comprise metal rings disposed at the inner sides of both the lower DBR stack and the upper DBR stack in proximity to the quantum well structure, and the one or more metal vias comprise multiple metal vias passing through both of the lower and the upper DBR stacks so as to connect the metal rings to respective electrical contacts. New
11-12. Canceled
Canceled
A method for fabricating an optoelectronic device, the method comprising: depositing a set of epitaxial layers comprising I II-V semiconductor materials on a I II -V substrate so as to form a quantum well structure; forming a confinement layer over the quantum well structure; depositing alternating first dielectric and semiconductor layers so as to form a lower distributed Bragg-reflector (DBR) stack; bonding the I II -V substrate to a carrier substrate so that the lower DBR stack is positioned between the quantum well structure and the carrier substrate, and then removing the I II -V substrate; after removing the I II -V substrate, depositing alternating second dielectric and semiconductor layers over the set of epitaxial layers so as to form an upper DBR stack; and coupling electrodes to apply an excitation current to the quantum well structure by depositing a metal ring over at least one side of the quantum well structure at an inner side of at least one of the DBR stacks, before forming the upper DBR stack, and forming one or more metal vias passing through the at least one of the DBR stacks so as to connect the metal ring at the inner side of the at least one of the DBR stacks to an electrical contact on an outer side of the at least one of the DBR stacks. Currently amended
The method according to claim 13, wherein forming the confinement layer comprises laterally etching one of the epitaxial layers, so that the confinement layer comprises a central part comprising a I II -V semiconductor material and a peripheral part comprising a dielectric material surrounding the central part. Original
The method according to claim 13, wherein forming the confinement layer patterning and then regrowing one of the epitaxial layers so as to form a buried tunnel junction in a central part of the one of the epitaxial layers. Original
The method according to claim 13, wherein depositing the alternating first dielectric and semiconductor layers comprises forming the lower DBR stack on the carrier substrate, and wherein bonding the I II-V substrate comprises bonding the set of epitaxial layers to the lower DBR stack on the carrier substrate. Original
The method according to claim 13, wherein depositing the alternating first dielectric and semiconductor layers comprises forming the lower DBR stack on the I II -V substrate over the set of epitaxial layers and the confinement layer, and wherein bonding the I II-V substrate comprises bonding lower DBR stack on the I II-V substrate to the carrier substrate. Original
The method according to claim 13, wherein the I II -V semiconductor materials deposited in the set of epitaxial layers are selected from a group of materials consisting of indium phosphide (InP), indium-gallium- arsenide (InGaAs), indium-gallium-arsenide-phosphide (InGaAsP), aluminum-gallium-indium-arsenide (AlGaInAs) and aluminum-gallium-arsenide-antimonide (AlGaAsSb). Original
The method according to claim 13, wherein coupling the electrodes comprises depositing metal rings at the inner sides of both the lower DBR stack and the upper DBR stack in proximity to the quantum well structure, and forming multiple metal vias passing through both of the lower and the upper DBR stacks so as to connect the metal rings to respective electrical contacts. New
18-19. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
InP-based VCSEL (vertical-cavity surface-emitting laser)
Materials described outside the worked examples.
III-V semiconductor
dielectric material
semiconductor (DBR layer)
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
VCSEL emission wavelength range | 1350–2000 nm | — |
Thickness | 1–15 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,322,910Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An optoelectronic device, comprising: a carrier substrate; a lower distributed Bragg-reflector (DBR) stack disposed on an area of the substrate and comprising alternating first dielectric and semiconductor layers; a set of epitaxial layers disposed over the lower DBR, wherein the set of epitaxial layers comprises one or more III -V semiconductor materials and defines: a quantum well structure; and a confinement layer; an upper DBR stack disposed over the set of epitaxial layers and comprising alternating second dielectric and semiconductor layers; electrodes coupled to apply an excitation current to the quantum well structure, wherein at least one of the electrodes comprises a metal ring disposed at an inner side of at least one of the DBR stacks in proximity to the quantum well structure; and one or more metal vias passing through the at least one of the DBR stacks so as to connect the metal ring at the inner side of the at least one of the DBR stacks to an electrical contact on an outer side of the at least one of the DBR stacks. Currently amended
The optoelectronic device according to claim 1, wherein the carrier substrate comprises a silicon (Si) wafer. Original
The optoelectronic device according to claim 1, wherein the alternating first dielectric and semiconductor layers comprise alternating layers of silicon dioxide (SiO 2) and amorphous silicon (a-Si). Original
The optoelectronic device according to claim 1, wherein the alternating first dielectric and semiconductor layers comprise alternating layers of aluminum nitride (AlN) and a-Si. Original
The optoelectronic device according to claim 1, wherein the one or more I II-V semiconductor materials are selected from a group of materials consisting of indium phosphide (InP), indium-gallium-arsenide (InGaAs), indium-gallium-arsenide- phosphide (InGaAsP), aluminum-gallium-indium-arsenide (AlGaInAs) and aluminum-gallium-arsenide-antimonide (AlGaAsSb).
The optoelectronic device according to claim 1, wherein the confinement layer comprises: a central part comprising a I II -V semiconductor material; and a peripheral part surrounding the central part and comprising a dielectric material. Original
The optoelectronic device according to claim 1, wherein the confinement layer comprises a buried tunnel junction. Original
The optoelectronic device according to claim 1, wherein the second dielectric and semiconductor layers comprise alternating layers of SiO 2 and amorphous silicon. Original
The optoelectronic device according to claim 1, wherein the electrodes comprise metal rings disposed at the inner sides of both the lower DBR stack and the upper DBR stack in proximity to the quantum well structure, and the one or more metal vias comprise multiple metal vias passing through both of the lower and the upper DBR stacks so as to connect the metal rings to respective electrical contacts. New
11-12. Canceled
Canceled
A method for fabricating an optoelectronic device, the method comprising: depositing a set of epitaxial layers comprising I II-V semiconductor materials on a I II -V substrate so as to form a quantum well structure; forming a confinement layer over the quantum well structure; depositing alternating first dielectric and semiconductor layers so as to form a lower distributed Bragg-reflector (DBR) stack; bonding the I II -V substrate to a carrier substrate so that the lower DBR stack is positioned between the quantum well structure and the carrier substrate, and then removing the I II -V substrate; after removing the I II -V substrate, depositing alternating second dielectric and semiconductor layers over the set of epitaxial layers so as to form an upper DBR stack; and coupling electrodes to apply an excitation current to the quantum well structure by depositing a metal ring over at least one side of the quantum well structure at an inner side of at least one of the DBR stacks, before forming the upper DBR stack, and forming one or more metal vias passing through the at least one of the DBR stacks so as to connect the metal ring at the inner side of the at least one of the DBR stacks to an electrical contact on an outer side of the at least one of the DBR stacks. Currently amended
The method according to claim 13, wherein forming the confinement layer comprises laterally etching one of the epitaxial layers, so that the confinement layer comprises a central part comprising a I II -V semiconductor material and a peripheral part comprising a dielectric material surrounding the central part. Original
The method according to claim 13, wherein forming the confinement layer patterning and then regrowing one of the epitaxial layers so as to form a buried tunnel junction in a central part of the one of the epitaxial layers. Original
The method according to claim 13, wherein depositing the alternating first dielectric and semiconductor layers comprises forming the lower DBR stack on the carrier substrate, and wherein bonding the I II-V substrate comprises bonding the set of epitaxial layers to the lower DBR stack on the carrier substrate. Original
The method according to claim 13, wherein depositing the alternating first dielectric and semiconductor layers comprises forming the lower DBR stack on the I II -V substrate over the set of epitaxial layers and the confinement layer, and wherein bonding the I II-V substrate comprises bonding lower DBR stack on the I II-V substrate to the carrier substrate. Original
The method according to claim 13, wherein the I II -V semiconductor materials deposited in the set of epitaxial layers are selected from a group of materials consisting of indium phosphide (InP), indium-gallium- arsenide (InGaAs), indium-gallium-arsenide-phosphide (InGaAsP), aluminum-gallium-indium-arsenide (AlGaInAs) and aluminum-gallium-arsenide-antimonide (AlGaAsSb). Original
The method according to claim 13, wherein coupling the electrodes comprises depositing metal rings at the inner sides of both the lower DBR stack and the upper DBR stack in proximity to the quantum well structure, and forming multiple metal vias passing through both of the lower and the upper DBR stacks so as to connect the metal rings to respective electrical contacts. New
18-19. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
InP-based VCSEL (vertical-cavity surface-emitting laser)
Materials described outside the worked examples.
III-V semiconductor
dielectric material
semiconductor (DBR layer)
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
VCSEL emission wavelength range | 1350–2000 nm | — |
Thickness | 1–15 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,322,910Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An optoelectronic device, comprising: a carrier substrate; a lower distributed Bragg-reflector (DBR) stack disposed on an area of the substrate and comprising alternating first dielectric and semiconductor layers; a set of epitaxial layers disposed over the lower DBR, wherein the set of epitaxial layers comprises one or more III -V semiconductor materials and defines: a quantum well structure; and a confinement layer; an upper DBR stack disposed over the set of epitaxial layers and comprising alternating second dielectric and semiconductor layers; electrodes coupled to apply an excitation current to the quantum well structure, wherein at least one of the electrodes comprises a metal ring disposed at an inner side of at least one of the DBR stacks in proximity to the quantum well structure; and one or more metal vias passing through the at least one of the DBR stacks so as to connect the metal ring at the inner side of the at least one of the DBR stacks to an electrical contact on an outer side of the at least one of the DBR stacks. Currently amended
The optoelectronic device according to claim 1, wherein the carrier substrate comprises a silicon (Si) wafer. Original
The optoelectronic device according to claim 1, wherein the alternating first dielectric and semiconductor layers comprise alternating layers of silicon dioxide (SiO 2) and amorphous silicon (a-Si). Original
The optoelectronic device according to claim 1, wherein the alternating first dielectric and semiconductor layers comprise alternating layers of aluminum nitride (AlN) and a-Si. Original
The optoelectronic device according to claim 1, wherein the one or more I II-V semiconductor materials are selected from a group of materials consisting of indium phosphide (InP), indium-gallium-arsenide (InGaAs), indium-gallium-arsenide- phosphide (InGaAsP), aluminum-gallium-indium-arsenide (AlGaInAs) and aluminum-gallium-arsenide-antimonide (AlGaAsSb).
The optoelectronic device according to claim 1, wherein the confinement layer comprises: a central part comprising a I II -V semiconductor material; and a peripheral part surrounding the central part and comprising a dielectric material. Original
The optoelectronic device according to claim 1, wherein the confinement layer comprises a buried tunnel junction. Original
The optoelectronic device according to claim 1, wherein the second dielectric and semiconductor layers comprise alternating layers of SiO 2 and amorphous silicon. Original
The optoelectronic device according to claim 1, wherein the electrodes comprise metal rings disposed at the inner sides of both the lower DBR stack and the upper DBR stack in proximity to the quantum well structure, and the one or more metal vias comprise multiple metal vias passing through both of the lower and the upper DBR stacks so as to connect the metal rings to respective electrical contacts. New
11-12. Canceled
Canceled
A method for fabricating an optoelectronic device, the method comprising: depositing a set of epitaxial layers comprising I II-V semiconductor materials on a I II -V substrate so as to form a quantum well structure; forming a confinement layer over the quantum well structure; depositing alternating first dielectric and semiconductor layers so as to form a lower distributed Bragg-reflector (DBR) stack; bonding the I II -V substrate to a carrier substrate so that the lower DBR stack is positioned between the quantum well structure and the carrier substrate, and then removing the I II -V substrate; after removing the I II -V substrate, depositing alternating second dielectric and semiconductor layers over the set of epitaxial layers so as to form an upper DBR stack; and coupling electrodes to apply an excitation current to the quantum well structure by depositing a metal ring over at least one side of the quantum well structure at an inner side of at least one of the DBR stacks, before forming the upper DBR stack, and forming one or more metal vias passing through the at least one of the DBR stacks so as to connect the metal ring at the inner side of the at least one of the DBR stacks to an electrical contact on an outer side of the at least one of the DBR stacks. Currently amended
The method according to claim 13, wherein forming the confinement layer comprises laterally etching one of the epitaxial layers, so that the confinement layer comprises a central part comprising a I II -V semiconductor material and a peripheral part comprising a dielectric material surrounding the central part. Original
The method according to claim 13, wherein forming the confinement layer patterning and then regrowing one of the epitaxial layers so as to form a buried tunnel junction in a central part of the one of the epitaxial layers. Original
The method according to claim 13, wherein depositing the alternating first dielectric and semiconductor layers comprises forming the lower DBR stack on the carrier substrate, and wherein bonding the I II-V substrate comprises bonding the set of epitaxial layers to the lower DBR stack on the carrier substrate. Original
The method according to claim 13, wherein depositing the alternating first dielectric and semiconductor layers comprises forming the lower DBR stack on the I II -V substrate over the set of epitaxial layers and the confinement layer, and wherein bonding the I II-V substrate comprises bonding lower DBR stack on the I II-V substrate to the carrier substrate. Original
The method according to claim 13, wherein the I II -V semiconductor materials deposited in the set of epitaxial layers are selected from a group of materials consisting of indium phosphide (InP), indium-gallium- arsenide (InGaAs), indium-gallium-arsenide-phosphide (InGaAsP), aluminum-gallium-indium-arsenide (AlGaInAs) and aluminum-gallium-arsenide-antimonide (AlGaAsSb). Original
The method according to claim 13, wherein coupling the electrodes comprises depositing metal rings at the inner sides of both the lower DBR stack and the upper DBR stack in proximity to the quantum well structure, and forming multiple metal vias passing through both of the lower and the upper DBR stacks so as to connect the metal rings to respective electrical contacts. New
18-19. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
InP-based VCSEL (vertical-cavity surface-emitting laser)
Materials described outside the worked examples.
III-V semiconductor
dielectric material
semiconductor (DBR layer)
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
VCSEL emission wavelength range | 1350–2000 nm | — |
Thickness | 1–15 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,322,910Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An optoelectronic device, comprising: a carrier substrate; a lower distributed Bragg-reflector (DBR) stack disposed on an area of the substrate and comprising alternating first dielectric and semiconductor layers; a set of epitaxial layers disposed over the lower DBR, wherein the set of epitaxial layers comprises one or more III -V semiconductor materials and defines: a quantum well structure; and a confinement layer; an upper DBR stack disposed over the set of epitaxial layers and comprising alternating second dielectric and semiconductor layers; electrodes coupled to apply an excitation current to the quantum well structure, wherein at least one of the electrodes comprises a metal ring disposed at an inner side of at least one of the DBR stacks in proximity to the quantum well structure; and one or more metal vias passing through the at least one of the DBR stacks so as to connect the metal ring at the inner side of the at least one of the DBR stacks to an electrical contact on an outer side of the at least one of the DBR stacks. Currently amended
The optoelectronic device according to claim 1, wherein the carrier substrate comprises a silicon (Si) wafer. Original
The optoelectronic device according to claim 1, wherein the alternating first dielectric and semiconductor layers comprise alternating layers of silicon dioxide (SiO 2) and amorphous silicon (a-Si). Original
The optoelectronic device according to claim 1, wherein the alternating first dielectric and semiconductor layers comprise alternating layers of aluminum nitride (AlN) and a-Si. Original
The optoelectronic device according to claim 1, wherein the one or more I II-V semiconductor materials are selected from a group of materials consisting of indium phosphide (InP), indium-gallium-arsenide (InGaAs), indium-gallium-arsenide- phosphide (InGaAsP), aluminum-gallium-indium-arsenide (AlGaInAs) and aluminum-gallium-arsenide-antimonide (AlGaAsSb).
The optoelectronic device according to claim 1, wherein the confinement layer comprises: a central part comprising a I II -V semiconductor material; and a peripheral part surrounding the central part and comprising a dielectric material. Original
The optoelectronic device according to claim 1, wherein the confinement layer comprises a buried tunnel junction. Original
The optoelectronic device according to claim 1, wherein the second dielectric and semiconductor layers comprise alternating layers of SiO 2 and amorphous silicon. Original
The optoelectronic device according to claim 1, wherein the electrodes comprise metal rings disposed at the inner sides of both the lower DBR stack and the upper DBR stack in proximity to the quantum well structure, and the one or more metal vias comprise multiple metal vias passing through both of the lower and the upper DBR stacks so as to connect the metal rings to respective electrical contacts. New
11-12. Canceled
Canceled
A method for fabricating an optoelectronic device, the method comprising: depositing a set of epitaxial layers comprising I II-V semiconductor materials on a I II -V substrate so as to form a quantum well structure; forming a confinement layer over the quantum well structure; depositing alternating first dielectric and semiconductor layers so as to form a lower distributed Bragg-reflector (DBR) stack; bonding the I II -V substrate to a carrier substrate so that the lower DBR stack is positioned between the quantum well structure and the carrier substrate, and then removing the I II -V substrate; after removing the I II -V substrate, depositing alternating second dielectric and semiconductor layers over the set of epitaxial layers so as to form an upper DBR stack; and coupling electrodes to apply an excitation current to the quantum well structure by depositing a metal ring over at least one side of the quantum well structure at an inner side of at least one of the DBR stacks, before forming the upper DBR stack, and forming one or more metal vias passing through the at least one of the DBR stacks so as to connect the metal ring at the inner side of the at least one of the DBR stacks to an electrical contact on an outer side of the at least one of the DBR stacks. Currently amended
The method according to claim 13, wherein forming the confinement layer comprises laterally etching one of the epitaxial layers, so that the confinement layer comprises a central part comprising a I II -V semiconductor material and a peripheral part comprising a dielectric material surrounding the central part. Original
The method according to claim 13, wherein forming the confinement layer patterning and then regrowing one of the epitaxial layers so as to form a buried tunnel junction in a central part of the one of the epitaxial layers. Original
The method according to claim 13, wherein depositing the alternating first dielectric and semiconductor layers comprises forming the lower DBR stack on the carrier substrate, and wherein bonding the I II-V substrate comprises bonding the set of epitaxial layers to the lower DBR stack on the carrier substrate. Original
The method according to claim 13, wherein depositing the alternating first dielectric and semiconductor layers comprises forming the lower DBR stack on the I II -V substrate over the set of epitaxial layers and the confinement layer, and wherein bonding the I II-V substrate comprises bonding lower DBR stack on the I II-V substrate to the carrier substrate. Original
The method according to claim 13, wherein the I II -V semiconductor materials deposited in the set of epitaxial layers are selected from a group of materials consisting of indium phosphide (InP), indium-gallium- arsenide (InGaAs), indium-gallium-arsenide-phosphide (InGaAsP), aluminum-gallium-indium-arsenide (AlGaInAs) and aluminum-gallium-arsenide-antimonide (AlGaAsSb). Original
The method according to claim 13, wherein coupling the electrodes comprises depositing metal rings at the inner sides of both the lower DBR stack and the upper DBR stack in proximity to the quantum well structure, and forming multiple metal vias passing through both of the lower and the upper DBR stacks so as to connect the metal rings to respective electrical contacts. New
18-19. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
InP-based VCSEL (vertical-cavity surface-emitting laser)
Materials described outside the worked examples.
III-V semiconductor
dielectric material
semiconductor (DBR layer)
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
VCSEL emission wavelength range | 1350–2000 nm | — |
Thickness | 1–15 nm |
Related documents with shared materials, methods, properties, or citations.
silicon
Si
silicon dioxide
SiO₂
amorphous silicon
a-Si
aluminum nitride
AlN
indium phosphide
InP
indium-gallium-arsenide
InGaAs
indium-gallium-arsenide-phosphide
InGaAsP
aluminum-gallium-indium-arsenide
AlGaInAs
aluminum-gallium-arsenide-antimonide
AlGaAsSb
aluminum oxide
Al₂O₃
| — |
Thickness | ≤ 500 nm | — |
silicon
Si
silicon dioxide
SiO₂
amorphous silicon
a-Si
aluminum nitride
AlN
indium phosphide
InP
indium-gallium-arsenide
InGaAs
indium-gallium-arsenide-phosphide
InGaAsP
aluminum-gallium-indium-arsenide
AlGaInAs
aluminum-gallium-arsenide-antimonide
AlGaAsSb
aluminum oxide
Al₂O₃
| — |
Thickness | ≤ 500 nm | — |
silicon
Si
silicon dioxide
SiO₂
amorphous silicon
a-Si
aluminum nitride
AlN
indium phosphide
InP
indium-gallium-arsenide
InGaAs
indium-gallium-arsenide-phosphide
InGaAsP
aluminum-gallium-indium-arsenide
AlGaInAs
aluminum-gallium-arsenide-antimonide
AlGaAsSb
aluminum oxide
Al₂O₃
| — |
Thickness | ≤ 500 nm | — |
silicon
Si
silicon dioxide
SiO₂
amorphous silicon
a-Si
aluminum nitride
AlN
indium phosphide
InP
indium-gallium-arsenide
InGaAs
indium-gallium-arsenide-phosphide
InGaAsP
aluminum-gallium-indium-arsenide
AlGaInAs
aluminum-gallium-arsenide-antimonide
AlGaAsSb
aluminum oxide
Al₂O₃
| — |
Thickness | ≤ 500 nm | — |