Patent
US 9,812,527GROWTH OF SEMICONDUCTORS ON HETERO-SUBSTRATES USING GRAPHENE AS AN INTERFACIAL LAYER
Yong ZHANG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,812,527Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1 A, 1B, and 1 C are diagrammatic representations (through a common cross sectional view) of a substrate and a graphene interfacial layer according to one embodiment.
Figure 2 illustrates a Raman spectrum of Si grown on graphite compared to that of Si single crystal according to one embodiment.
Figure 3 illustrates SEM images of Si grown on a graphite substrate with unintended steps, according to one embodiment.
Figure 4 presents an AFM image of thin Si structures grown on a graphite substrate according to one embodiment.
Figure 5 illustrates a SEM image of Si grown on graphite wafer according to one embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) An electronic device, comprising: a substrate; a crystalline graphene layer deposited on the substrate; and a semiconductor material deposited on the crystalline graphene layer so that epitaxial layers of the semiconductor material grow on the crystalline graphene layer, wherein the crystalline graphene layer is a graphene layer that has not been intentionally or unintentionally modified to increase the number of defects that function as nucleation sites. Currently amended
(Cu rr ently Amended) The electronic device as in claim 1, wherein the crystalline graphene layer consists of a single atomic layer of carbon. Currently amended
The electronic device as in claim 1, wherein the crystalline graphene layer comprises a plurality of layers of crystalline graphene. Original
The electronic device as in claim 1, wherein the substrate comprises one of a SiO 2/Si substrate, a glass substrate, a metal substrate, or a ceramic substrate. Original
The electronic device as in claim 1, wherein the substrate comprises a graphite substrate. Original
The electronic device as in claim 1, wherein the semiconductor material comprises silicon. Original
The electronic device as in claim 1, wherein the semiconductor material comprises silicene. Original
The electronic device as in claim 1, wherein the substrate is one that can withstand a growth temperature without a limitation matching condition required for epitaxial growth. Original
The method of claim 1 1, further comprising rotating the substrate during the depositing the crystalline graphene layer. Currently amended
The electronic device as in claim t, wherein the semiconductor material comprises a crystalline material. Original
The electronic device as in claim 9, wherein the crystalline material has a 2-dimensional Si structure. Original
A method of growing semiconductors on hetero- substrates using graphene as an interfacial layer, the method comprising: providing a substrate; depositing a crystalline graphene layer on the substrate; depositing, using one of e-beam evaporation, molecular beam epitaxy or atomic layer deposition, a silicon epitaxial layer on the crystalline graphene layer so that the silicon epitaxial layer grows on the crystalline graphene layer, wherein the crystalline graphene layer is a graphene layer that has not been intentionally or unintentionally modified to increase the number of defects that function as nucleation sites. Currently amended
The method of claim 11, further comprising providing liquid nitrogen in walls of a growth chamber during deposition of the silicon epitaxial layer on the g raphene layer. Original
The method of claim 11, further comprising heating the substrate to a predetermined temperature so that absorbed Si atoms nucleate and grow into a uniformly crystalized atomic structure. Original
The method of claim 11, wherein the substrate comprises SiO 2/Si substrate. Original
The method of claim 11, wherein the substrate comprises one of a glass substrate, a metal substrate, or a ceramic substrate. Original
The method of claim 11, wherein the substrate is 300nm in thickness. Original
(Cu rr ently Amended) A method comprising: providing a substrate; transferring a crystalline graphene layer on the substrate; and depositing, using one of e-beam evaporation, molecular beam epitaxy or atomic layer deposition, a silicon epitaxial layer on the crystalline graphene layer so that the silicon epitaxial layer grows on the crystalline graphene layer, wherein the crystalline graphene layer is a graphene layer that has not been intentionally or unintentionally modified to increase the number of defects that function as nucleation sites. Currently amended
The method of claim 19, wherein the substrate comprises one of a SiO 2/Si substrate or quartz substrate. Original
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor heterostructure on graphene interfacial layer
Materials described outside the worked examples.
crystalline graphene
C
silicon epitaxial layer
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–400 nm | — |
Pressure |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,812,527Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1 A, 1B, and 1 C are diagrammatic representations (through a common cross sectional view) of a substrate and a graphene interfacial layer according to one embodiment.
Figure 2 illustrates a Raman spectrum of Si grown on graphite compared to that of Si single crystal according to one embodiment.
Figure 3 illustrates SEM images of Si grown on a graphite substrate with unintended steps, according to one embodiment.
Figure 4 presents an AFM image of thin Si structures grown on a graphite substrate according to one embodiment.
Figure 5 illustrates a SEM image of Si grown on graphite wafer according to one embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) An electronic device, comprising: a substrate; a crystalline graphene layer deposited on the substrate; and a semiconductor material deposited on the crystalline graphene layer so that epitaxial layers of the semiconductor material grow on the crystalline graphene layer, wherein the crystalline graphene layer is a graphene layer that has not been intentionally or unintentionally modified to increase the number of defects that function as nucleation sites. Currently amended
(Cu rr ently Amended) The electronic device as in claim 1, wherein the crystalline graphene layer consists of a single atomic layer of carbon. Currently amended
The electronic device as in claim 1, wherein the crystalline graphene layer comprises a plurality of layers of crystalline graphene. Original
The electronic device as in claim 1, wherein the substrate comprises one of a SiO 2/Si substrate, a glass substrate, a metal substrate, or a ceramic substrate. Original
The electronic device as in claim 1, wherein the substrate comprises a graphite substrate. Original
The electronic device as in claim 1, wherein the semiconductor material comprises silicon. Original
The electronic device as in claim 1, wherein the semiconductor material comprises silicene. Original
The electronic device as in claim 1, wherein the substrate is one that can withstand a growth temperature without a limitation matching condition required for epitaxial growth. Original
The method of claim 1 1, further comprising rotating the substrate during the depositing the crystalline graphene layer. Currently amended
The electronic device as in claim t, wherein the semiconductor material comprises a crystalline material. Original
The electronic device as in claim 9, wherein the crystalline material has a 2-dimensional Si structure. Original
A method of growing semiconductors on hetero- substrates using graphene as an interfacial layer, the method comprising: providing a substrate; depositing a crystalline graphene layer on the substrate; depositing, using one of e-beam evaporation, molecular beam epitaxy or atomic layer deposition, a silicon epitaxial layer on the crystalline graphene layer so that the silicon epitaxial layer grows on the crystalline graphene layer, wherein the crystalline graphene layer is a graphene layer that has not been intentionally or unintentionally modified to increase the number of defects that function as nucleation sites. Currently amended
The method of claim 11, further comprising providing liquid nitrogen in walls of a growth chamber during deposition of the silicon epitaxial layer on the g raphene layer. Original
The method of claim 11, further comprising heating the substrate to a predetermined temperature so that absorbed Si atoms nucleate and grow into a uniformly crystalized atomic structure. Original
The method of claim 11, wherein the substrate comprises SiO 2/Si substrate. Original
The method of claim 11, wherein the substrate comprises one of a glass substrate, a metal substrate, or a ceramic substrate. Original
The method of claim 11, wherein the substrate is 300nm in thickness. Original
(Cu rr ently Amended) A method comprising: providing a substrate; transferring a crystalline graphene layer on the substrate; and depositing, using one of e-beam evaporation, molecular beam epitaxy or atomic layer deposition, a silicon epitaxial layer on the crystalline graphene layer so that the silicon epitaxial layer grows on the crystalline graphene layer, wherein the crystalline graphene layer is a graphene layer that has not been intentionally or unintentionally modified to increase the number of defects that function as nucleation sites. Currently amended
The method of claim 19, wherein the substrate comprises one of a SiO 2/Si substrate or quartz substrate. Original
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor heterostructure on graphene interfacial layer
Materials described outside the worked examples.
crystalline graphene
C
silicon epitaxial layer
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–400 nm | — |
Pressure |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,812,527Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1 A, 1B, and 1 C are diagrammatic representations (through a common cross sectional view) of a substrate and a graphene interfacial layer according to one embodiment.
Figure 2 illustrates a Raman spectrum of Si grown on graphite compared to that of Si single crystal according to one embodiment.
Figure 3 illustrates SEM images of Si grown on a graphite substrate with unintended steps, according to one embodiment.
Figure 4 presents an AFM image of thin Si structures grown on a graphite substrate according to one embodiment.
Figure 5 illustrates a SEM image of Si grown on graphite wafer according to one embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) An electronic device, comprising: a substrate; a crystalline graphene layer deposited on the substrate; and a semiconductor material deposited on the crystalline graphene layer so that epitaxial layers of the semiconductor material grow on the crystalline graphene layer, wherein the crystalline graphene layer is a graphene layer that has not been intentionally or unintentionally modified to increase the number of defects that function as nucleation sites. Currently amended
(Cu rr ently Amended) The electronic device as in claim 1, wherein the crystalline graphene layer consists of a single atomic layer of carbon. Currently amended
The electronic device as in claim 1, wherein the crystalline graphene layer comprises a plurality of layers of crystalline graphene. Original
The electronic device as in claim 1, wherein the substrate comprises one of a SiO 2/Si substrate, a glass substrate, a metal substrate, or a ceramic substrate. Original
The electronic device as in claim 1, wherein the substrate comprises a graphite substrate. Original
The electronic device as in claim 1, wherein the semiconductor material comprises silicon. Original
The electronic device as in claim 1, wherein the semiconductor material comprises silicene. Original
The electronic device as in claim 1, wherein the substrate is one that can withstand a growth temperature without a limitation matching condition required for epitaxial growth. Original
The method of claim 1 1, further comprising rotating the substrate during the depositing the crystalline graphene layer. Currently amended
The electronic device as in claim t, wherein the semiconductor material comprises a crystalline material. Original
The electronic device as in claim 9, wherein the crystalline material has a 2-dimensional Si structure. Original
A method of growing semiconductors on hetero- substrates using graphene as an interfacial layer, the method comprising: providing a substrate; depositing a crystalline graphene layer on the substrate; depositing, using one of e-beam evaporation, molecular beam epitaxy or atomic layer deposition, a silicon epitaxial layer on the crystalline graphene layer so that the silicon epitaxial layer grows on the crystalline graphene layer, wherein the crystalline graphene layer is a graphene layer that has not been intentionally or unintentionally modified to increase the number of defects that function as nucleation sites. Currently amended
The method of claim 11, further comprising providing liquid nitrogen in walls of a growth chamber during deposition of the silicon epitaxial layer on the g raphene layer. Original
The method of claim 11, further comprising heating the substrate to a predetermined temperature so that absorbed Si atoms nucleate and grow into a uniformly crystalized atomic structure. Original
The method of claim 11, wherein the substrate comprises SiO 2/Si substrate. Original
The method of claim 11, wherein the substrate comprises one of a glass substrate, a metal substrate, or a ceramic substrate. Original
The method of claim 11, wherein the substrate is 300nm in thickness. Original
(Cu rr ently Amended) A method comprising: providing a substrate; transferring a crystalline graphene layer on the substrate; and depositing, using one of e-beam evaporation, molecular beam epitaxy or atomic layer deposition, a silicon epitaxial layer on the crystalline graphene layer so that the silicon epitaxial layer grows on the crystalline graphene layer, wherein the crystalline graphene layer is a graphene layer that has not been intentionally or unintentionally modified to increase the number of defects that function as nucleation sites. Currently amended
The method of claim 19, wherein the substrate comprises one of a SiO 2/Si substrate or quartz substrate. Original
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor heterostructure on graphene interfacial layer
Materials described outside the worked examples.
crystalline graphene
C
silicon epitaxial layer
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–400 nm | — |
Pressure |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,812,527Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1 A, 1B, and 1 C are diagrammatic representations (through a common cross sectional view) of a substrate and a graphene interfacial layer according to one embodiment.
Figure 2 illustrates a Raman spectrum of Si grown on graphite compared to that of Si single crystal according to one embodiment.
Figure 3 illustrates SEM images of Si grown on a graphite substrate with unintended steps, according to one embodiment.
Figure 4 presents an AFM image of thin Si structures grown on a graphite substrate according to one embodiment.
Figure 5 illustrates a SEM image of Si grown on graphite wafer according to one embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) An electronic device, comprising: a substrate; a crystalline graphene layer deposited on the substrate; and a semiconductor material deposited on the crystalline graphene layer so that epitaxial layers of the semiconductor material grow on the crystalline graphene layer, wherein the crystalline graphene layer is a graphene layer that has not been intentionally or unintentionally modified to increase the number of defects that function as nucleation sites. Currently amended
(Cu rr ently Amended) The electronic device as in claim 1, wherein the crystalline graphene layer consists of a single atomic layer of carbon. Currently amended
The electronic device as in claim 1, wherein the crystalline graphene layer comprises a plurality of layers of crystalline graphene. Original
The electronic device as in claim 1, wherein the substrate comprises one of a SiO 2/Si substrate, a glass substrate, a metal substrate, or a ceramic substrate. Original
The electronic device as in claim 1, wherein the substrate comprises a graphite substrate. Original
The electronic device as in claim 1, wherein the semiconductor material comprises silicon. Original
The electronic device as in claim 1, wherein the semiconductor material comprises silicene. Original
The electronic device as in claim 1, wherein the substrate is one that can withstand a growth temperature without a limitation matching condition required for epitaxial growth. Original
The method of claim 1 1, further comprising rotating the substrate during the depositing the crystalline graphene layer. Currently amended
The electronic device as in claim t, wherein the semiconductor material comprises a crystalline material. Original
The electronic device as in claim 9, wherein the crystalline material has a 2-dimensional Si structure. Original
A method of growing semiconductors on hetero- substrates using graphene as an interfacial layer, the method comprising: providing a substrate; depositing a crystalline graphene layer on the substrate; depositing, using one of e-beam evaporation, molecular beam epitaxy or atomic layer deposition, a silicon epitaxial layer on the crystalline graphene layer so that the silicon epitaxial layer grows on the crystalline graphene layer, wherein the crystalline graphene layer is a graphene layer that has not been intentionally or unintentionally modified to increase the number of defects that function as nucleation sites. Currently amended
The method of claim 11, further comprising providing liquid nitrogen in walls of a growth chamber during deposition of the silicon epitaxial layer on the g raphene layer. Original
The method of claim 11, further comprising heating the substrate to a predetermined temperature so that absorbed Si atoms nucleate and grow into a uniformly crystalized atomic structure. Original
The method of claim 11, wherein the substrate comprises SiO 2/Si substrate. Original
The method of claim 11, wherein the substrate comprises one of a glass substrate, a metal substrate, or a ceramic substrate. Original
The method of claim 11, wherein the substrate is 300nm in thickness. Original
(Cu rr ently Amended) A method comprising: providing a substrate; transferring a crystalline graphene layer on the substrate; and depositing, using one of e-beam evaporation, molecular beam epitaxy or atomic layer deposition, a silicon epitaxial layer on the crystalline graphene layer so that the silicon epitaxial layer grows on the crystalline graphene layer, wherein the crystalline graphene layer is a graphene layer that has not been intentionally or unintentionally modified to increase the number of defects that function as nucleation sites. Currently amended
The method of claim 19, wherein the substrate comprises one of a SiO 2/Si substrate or quartz substrate. Original
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor heterostructure on graphene interfacial layer
Materials described outside the worked examples.
crystalline graphene
C
silicon epitaxial layer
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–400 nm | — |
Pressure |
Related documents with shared materials, methods, properties, or citations.
SiO₂/Si substrate
glass substrate
metal substrate
ceramic substrate
quartz substrate
ZnSe thin-film
ZnSe
300nm SiO₂/Si substrate
| 10–10 Torr |
| — |
Thickness | 50–100 nm | — |
HETEROLITHIC MICROWAVE INTEGRATED CIRCUITS INCLUDING GALLIUM-NITRIDE DEVICES ON INTRINSIC SEMICONDUCTOR
SiO₂/Si substrate
glass substrate
metal substrate
ceramic substrate
quartz substrate
ZnSe thin-film
ZnSe
300nm SiO₂/Si substrate
| 10–10 Torr |
| — |
Thickness | 50–100 nm | — |
HETEROLITHIC MICROWAVE INTEGRATED CIRCUITS INCLUDING GALLIUM-NITRIDE DEVICES ON INTRINSIC SEMICONDUCTOR
SiO₂/Si substrate
glass substrate
metal substrate
ceramic substrate
quartz substrate
ZnSe thin-film
ZnSe
300nm SiO₂/Si substrate
| 10–10 Torr |
| — |
Thickness | 50–100 nm | — |
HETEROLITHIC MICROWAVE INTEGRATED CIRCUITS INCLUDING GALLIUM-NITRIDE DEVICES ON INTRINSIC SEMICONDUCTOR
SiO₂/Si substrate
glass substrate
metal substrate
ceramic substrate
quartz substrate
ZnSe thin-film
ZnSe
300nm SiO₂/Si substrate
| 10–10 Torr |
| — |
Thickness | 50–100 nm | — |
HETEROLITHIC MICROWAVE INTEGRATED CIRCUITS INCLUDING GALLIUM-NITRIDE DEVICES ON INTRINSIC SEMICONDUCTOR