Patent
US 8,716,766GRAPHENE SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, ORGANIC LIGHT EMITTING DISPLAY, AND MEMORY INCLUDING GRAPHENE SEMICONDUCTOR DEVICE
Chang Seung LEE
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 to 5 are schematic sectional views illustrating a method of manufacturing a graphene semiconductor device according to example embodiments. [0029]
FIG. 2, a transfer substrate 150 may be stuck to the multilayered member with an adhesive layer 160. In example embodiments, the transfer substrate 150 may be …
FIG. 3. Therefore, the first electrode 770 may serve as an anode of the switching diode, while the second electrode 780 may serve as a cathode of the switching …
FIG. 4, an insulating layer 220 may be deposited on a base substrate 210, and a graphene layer 230 may be then deposited on the insulating layer 220 to form …
FIG. 5, the two laminates 100 and 200 may be attached to each other such that the exposed surface of the semiconductor layer 130 in the process shown in
FIG. 6 is a schematic diagram of a graphene thin film diode according to example embodiments. [0030]
FIG. 7 is a graph showing a current-voltage characteristic of the graphene thin film diode shown in
FIGS. 8 to 12 are schematic sectional views illustrating a method of manufacturing a graphene thin film diode shown in
FIG. 9, portions of the conductor layer 440 and the semiconductor layer 430, which are left against (or, after) the etching, may become a first electrode 370 …
FIG. 10 contacts a surface of the graphene layer 355. In example embodiments, the gate electrode 330 may be aligned with the semiconductor member 360. [0093] …
FIG. 11, a subsidiary insulating layer 320 and a conductor layer (not shown) may be deposited in sequence on a base substrate 310. The subsidiary insulating …
FIG. 12, a laminate including the layers 360, 370, 460 and 450 shown in
FIG. 13 is a schematic diagram of a structure that forms at least a portion of a pixel in an OLED according to example embodiments. [0033]
FIG. 14 is a schematic diagram of another structure that forms at least a portion of a pixel in an OLED according to example embodiments. [0034]
FIG. 15 is a schematic diagram of a structure that forms at least a portion of a cell in an RRAM according to example embodiments. [0035]
FIG. 16 is a block diagram of a pixel of an OLED according to example embodiments. [0036]
FIG. 17 is an example equivalent circuit diagram of the pixel shown in
FIG. 18 is a block diagram of another pixel of an OLED according to example embodiments. [0038]
FIG. 19 is an example equivalent circuit diagram of the pixel shown in
FIG. 20 is a block diagram of a cell of a RRAM according to example embodiments. [0040]
FIG. 21 is an example equivalent circuit diagram of the cell shown in
FIG. 22 is a schematic layout view of an OLED according to example embodiments. [0042]
FIG. 23 is a schematically expanded layout view of a pixel of the OLED shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(ORIGINAL) A method of manufacturing a graphene semiconductor device, the method compris ing: forming a multilayered member inc lud in g a sacrificial substrate, a sac ri ficial layer, and a semiconductor layer deposited m sequence; forming a transfer substrate on the semiconductor layer; forming a first laminate including the transfer substrate and the semiconductor layer by removing the sacrificial layer to separate the sac n ficial substrate from the semiconductor layer; forming a second laminate by forming a graphene layer on a base substrate; combining the first laminate and the second laminate such that the semiconductor layer contacts the graphene layer; and remov in g the transfer substrate.
(ORIGINAL) The method of claim 1, wherein the semiconductor layer includes at least one of Si, GaAs, InP, GaP, and InAs.
(ORIGINAL) The method of claim 1, wherein the sacrificial layer includes at least one of SiO2, SiN, A 12O3, HfO 2, ZrO 2, A l GaAs, and A l As.
(ORIGINAL) The method of claim 1, wherein forming the multilayered member includes, depositing a conductor layer on the semiconductor layer; patterning the conductor layer to form a first electrode; and patterning the semiconductor layer to form a semiconductor member. U.S. App li cation No. 13/523,554 Atty. Dkt. No. 15639-000075-US Page 3 of 10 SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615501.7.463.347.2227.399.svg 0.173 5.88 Graph Black and white lam in ate and the second laminate includes contacting the semiconductor member with the graphene layer, and wherein the method further comprises forming a second electrode on an exposed surface of the graphene layer. SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615501.12.457.834.2224.884.svg 0.167 5.89 Graph Black and white lam in ate includes, forming a gate electrode on the base substrate; forming a gate insulating layer on the gate electrode and the base substrate; and forming the graphene layer on the gate insulating layer, and where in combining the first laminate and the second laminate includes aligning the gate electrode with the semiconductor member.
The method of claim 6, further comprising: forming a light emitting layer; and forming a third electrode on the light emitt in g layer, where in the light emitting layer is on the second electrode when the semiconductor layer includes an N-type semiconductor, and the light emitt in g layer is on the first electrode when the semiconductor layer includes a P-type semiconductor.
The method of claim 6, further comprising: form in g a resistive mate ri al layer and a third electrode on one of the first electrode and the second electrode, wherein the resistive material layer has a resistance that varies based on a voltage across ends of the resistive material layer.
(ORIGINAL) The method of claim 6, where in the base substrate in cludes an in sulator, and the gate electrode contacts the base substrate.
The method of claim 6, wherein the base substrate includes a semiconductor, and SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615502.2.1444.126.2202.183.svg 0.19 2.527 Graph Black and white Atty. Dkt. No. 15639-000075-US Page 4 of 10 forming the second laminate further includes form in g a subsidiary insulating layer between the base substrate and the gate electrode. original
. canceled
The device of claim 1413, wherein the semiconductor layer includes at least one of Si, GaAs, InP, GaP, and InAs.
A graphene semiconductor device, The-devee ofe laim11, further comprising: a gate electrode on a substrate; a gate insulat in g la y er on the gate electrode; a graphene member on the gate in sulat in g la yer; a semiconductor member oin ed with the graphene member; a first electrode on the semiconductor member; a second electrode on the graphene member; a light emitting layer on one of the first electrode and the second electrode; and a third electrode on the light emitting layer, wherein the second electrode is s p aced apart from the semiconductor member and the first electrode, the li ght emitting layer is on the second electrode when the semiconductor layer includes an N-type semiconductor, and the light emitting layer is on the first electrode when the semiconductor layer includes a P-type semiconductor.
A graphene sem i conductor device, T-he-4eviee ef elaim 1,further- comprising: a gate electrode on a substrate; a gate in sulat in g layer on the gate electrode; a graphene member on the gate insulat mn g la y er; a semiconductor member i oined with the graphene member; a first electrode on the semiconductor member; a second electrode on the graphene member; SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615503.5.1432.194.2194.291.svg 0.323 2.54 Graph Black and white U.S. Application No. 13/523,554 a resistive material layer on one of the first electrode and the second electrode; and a third electrode on the resistive material layer, where in the second electrode is spaced apart from the semiconductor member and the first electrode, and the resistive material layer has a resistance that varies based on a voltage across ends of the resistive material layer. SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615503.15.438.1078.2198.1128.svg 0.167 5.867 Chemistry Black and white substrate includes an insulator, and the gate electrode contacts the substrate.
(NE W) The device of claim 14, further comprising: a subsidiary insulating layer between the base substrate and the gate electrode, wherein the base substrate includes a semiconductor. END OF CLAIM LISTING THE REMAINDER OF THE PAGE HAS BEEN LEFT BLANK INTENTIONALLY
The device of claim -413, further comprising a subsidiary insulating layer between the base substrate and the gate electrode, wherein the substrate includes a semiconductor.
The device of claim -113, where in at least one of the first electrode and the second electrode is transparent or translucent.
An organic light emitting display, comprising: a switching unit including a graphene semiconductor device, wherein the switching unit has a first terminal, a second terminal, and a third terminal; a scanning li ne connected to the first terminal of the switching unit; a data line connected to the second terminal of the switching unit; and a li ght emitt in g unit connected to the third terminal of the switching unit, wherein the graphene semiconductor device in cludes, a gate electrode on a substrate, a gate insulat in g layer on the gate electrode, a graphene member on the gate insulating layer, a semiconductor member jo in ed with the graphene member, a first electrode on the semiconductor member, and a second electrode on the graphene member, wherein the second electrode is spaced apart from the semiconductor member and the first electrode. SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615504.3.1433.127.2193.184.svg 0.19 2.533 Graph Black and white Atty. Dkt. No. 15639-000075-US Page 6 of
An organic light emitting display, comp ri sing: a switching unit in cluding a graphene semiconductor device, wherein the switching unit includes a first terminal, a second terminal, and a third terminal; a scann m g line connected to the first terminal of the switching unit; a data line connected to the second terminal of the switching unit; a dr ivin g unit having a first terminal and a second terminal, wherein the first terminal of the driving u ni t is connected to the third terminal of the switching u nit; and a light emitting unit connected to the second terminal of the driving unit, wherein the graphene semiconductor device includes, a gate electrode on a substrate, a gate insulating layer on the gate electrode, a graphene member on the gate insulating layer, a semiconductor member joined with the graphene member, a first electrode on the semiconductor member, and a second electrode on the graphene member, wherein the second electrode is spaced apart from the semiconductor member and the first electrode.
A memory, comprising: a switching u ni t includ in g a graphene semiconductor device, wherein the switching unit includes a first terminal, a second terminal, and a third terminal; a word l in e connected to the first terminal of the switching u nit; a gate line connected to the second term in al of the switching unit; a resistive unit hav in g a first terminal and a second terminal, wherein the first terminal of the resistive unit is connected to the third terminal of the switching unit; and a bit line connected to the second terminal of the resistive unit, wherein the graphene semiconductor device includes, a gate electrode on a substrate, a gate insulating layer on the gate electrode, a graphene member on the gate insulating layer, a semiconductor member joined with the graphene member, a first electrode on the semiconductor member, and a second electrode on the graphene member, wherein the second electrode is spaced apart from the semiconductor member and the first electrode. U. S. Application No. 13/523,554 Atty. Dkt. No. 15639-000075-US Page 7 of
Layer stacks claimed or described, ordered top of device to substrate.
graphene semiconductor device (method)
graphene semiconductor device with light emitting layer
graphene semiconductor device with resistive material layer
organic light emitting display with graphene semiconductor switching unit
memory with graphene semiconductor switching unit
Materials described outside the worked examples.
graphene
sacrificial layer
semiconductor layer
silicon
Si
gallium arsenide
GaAs
indium phosphide
InP
gallium phosphide
GaP
indium arsenide
InAs
silicon dioxide
SiO₂
silicon nitride
SiN
aluminum oxide
Al₂O₃
hafnium dioxide
HfO₂
zirconium dioxide
ZrO₂
aluminum gallium arsenide
AlGaAs
aluminum arsenide
AlAs
light emitting layer
N-type semiconductor
resistive material layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a graph showing a current-voltage characteristic of the graphene thin film diode shown in
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE
P-GAN-DOWN MICRO-LED ON SEMI-POLAR ORIENTED GAN
SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS INCLUDING INDIUM GALLIUM NITRIDE, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND RELATED LIGHT EMITTING DEVICES
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 to 5 are schematic sectional views illustrating a method of manufacturing a graphene semiconductor device according to example embodiments. [0029]
FIG. 2, a transfer substrate 150 may be stuck to the multilayered member with an adhesive layer 160. In example embodiments, the transfer substrate 150 may be …
FIG. 3. Therefore, the first electrode 770 may serve as an anode of the switching diode, while the second electrode 780 may serve as a cathode of the switching …
FIG. 4, an insulating layer 220 may be deposited on a base substrate 210, and a graphene layer 230 may be then deposited on the insulating layer 220 to form …
FIG. 5, the two laminates 100 and 200 may be attached to each other such that the exposed surface of the semiconductor layer 130 in the process shown in
FIG. 6 is a schematic diagram of a graphene thin film diode according to example embodiments. [0030]
FIG. 7 is a graph showing a current-voltage characteristic of the graphene thin film diode shown in
FIGS. 8 to 12 are schematic sectional views illustrating a method of manufacturing a graphene thin film diode shown in
FIG. 9, portions of the conductor layer 440 and the semiconductor layer 430, which are left against (or, after) the etching, may become a first electrode 370 …
FIG. 10 contacts a surface of the graphene layer 355. In example embodiments, the gate electrode 330 may be aligned with the semiconductor member 360. [0093] …
FIG. 11, a subsidiary insulating layer 320 and a conductor layer (not shown) may be deposited in sequence on a base substrate 310. The subsidiary insulating …
FIG. 12, a laminate including the layers 360, 370, 460 and 450 shown in
FIG. 13 is a schematic diagram of a structure that forms at least a portion of a pixel in an OLED according to example embodiments. [0033]
FIG. 14 is a schematic diagram of another structure that forms at least a portion of a pixel in an OLED according to example embodiments. [0034]
FIG. 15 is a schematic diagram of a structure that forms at least a portion of a cell in an RRAM according to example embodiments. [0035]
FIG. 16 is a block diagram of a pixel of an OLED according to example embodiments. [0036]
FIG. 17 is an example equivalent circuit diagram of the pixel shown in
FIG. 18 is a block diagram of another pixel of an OLED according to example embodiments. [0038]
FIG. 19 is an example equivalent circuit diagram of the pixel shown in
FIG. 20 is a block diagram of a cell of a RRAM according to example embodiments. [0040]
FIG. 21 is an example equivalent circuit diagram of the cell shown in
FIG. 22 is a schematic layout view of an OLED according to example embodiments. [0042]
FIG. 23 is a schematically expanded layout view of a pixel of the OLED shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(ORIGINAL) A method of manufacturing a graphene semiconductor device, the method compris ing: forming a multilayered member inc lud in g a sacrificial substrate, a sac ri ficial layer, and a semiconductor layer deposited m sequence; forming a transfer substrate on the semiconductor layer; forming a first laminate including the transfer substrate and the semiconductor layer by removing the sacrificial layer to separate the sac n ficial substrate from the semiconductor layer; forming a second laminate by forming a graphene layer on a base substrate; combining the first laminate and the second laminate such that the semiconductor layer contacts the graphene layer; and remov in g the transfer substrate.
(ORIGINAL) The method of claim 1, wherein the semiconductor layer includes at least one of Si, GaAs, InP, GaP, and InAs.
(ORIGINAL) The method of claim 1, wherein the sacrificial layer includes at least one of SiO2, SiN, A 12O3, HfO 2, ZrO 2, A l GaAs, and A l As.
(ORIGINAL) The method of claim 1, wherein forming the multilayered member includes, depositing a conductor layer on the semiconductor layer; patterning the conductor layer to form a first electrode; and patterning the semiconductor layer to form a semiconductor member. U.S. App li cation No. 13/523,554 Atty. Dkt. No. 15639-000075-US Page 3 of 10 SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615501.7.463.347.2227.399.svg 0.173 5.88 Graph Black and white lam in ate and the second laminate includes contacting the semiconductor member with the graphene layer, and wherein the method further comprises forming a second electrode on an exposed surface of the graphene layer. SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615501.12.457.834.2224.884.svg 0.167 5.89 Graph Black and white lam in ate includes, forming a gate electrode on the base substrate; forming a gate insulating layer on the gate electrode and the base substrate; and forming the graphene layer on the gate insulating layer, and where in combining the first laminate and the second laminate includes aligning the gate electrode with the semiconductor member.
The method of claim 6, further comprising: forming a light emitting layer; and forming a third electrode on the light emitt in g layer, where in the light emitting layer is on the second electrode when the semiconductor layer includes an N-type semiconductor, and the light emitt in g layer is on the first electrode when the semiconductor layer includes a P-type semiconductor.
The method of claim 6, further comprising: form in g a resistive mate ri al layer and a third electrode on one of the first electrode and the second electrode, wherein the resistive material layer has a resistance that varies based on a voltage across ends of the resistive material layer.
(ORIGINAL) The method of claim 6, where in the base substrate in cludes an in sulator, and the gate electrode contacts the base substrate.
The method of claim 6, wherein the base substrate includes a semiconductor, and SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615502.2.1444.126.2202.183.svg 0.19 2.527 Graph Black and white Atty. Dkt. No. 15639-000075-US Page 4 of 10 forming the second laminate further includes form in g a subsidiary insulating layer between the base substrate and the gate electrode. original
. canceled
The device of claim 1413, wherein the semiconductor layer includes at least one of Si, GaAs, InP, GaP, and InAs.
A graphene semiconductor device, The-devee ofe laim11, further comprising: a gate electrode on a substrate; a gate insulat in g la y er on the gate electrode; a graphene member on the gate in sulat in g la yer; a semiconductor member oin ed with the graphene member; a first electrode on the semiconductor member; a second electrode on the graphene member; a light emitting layer on one of the first electrode and the second electrode; and a third electrode on the light emitting layer, wherein the second electrode is s p aced apart from the semiconductor member and the first electrode, the li ght emitting layer is on the second electrode when the semiconductor layer includes an N-type semiconductor, and the light emitting layer is on the first electrode when the semiconductor layer includes a P-type semiconductor.
A graphene sem i conductor device, T-he-4eviee ef elaim 1,further- comprising: a gate electrode on a substrate; a gate in sulat in g layer on the gate electrode; a graphene member on the gate insulat mn g la y er; a semiconductor member i oined with the graphene member; a first electrode on the semiconductor member; a second electrode on the graphene member; SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615503.5.1432.194.2194.291.svg 0.323 2.54 Graph Black and white U.S. Application No. 13/523,554 a resistive material layer on one of the first electrode and the second electrode; and a third electrode on the resistive material layer, where in the second electrode is spaced apart from the semiconductor member and the first electrode, and the resistive material layer has a resistance that varies based on a voltage across ends of the resistive material layer. SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615503.15.438.1078.2198.1128.svg 0.167 5.867 Chemistry Black and white substrate includes an insulator, and the gate electrode contacts the substrate.
(NE W) The device of claim 14, further comprising: a subsidiary insulating layer between the base substrate and the gate electrode, wherein the base substrate includes a semiconductor. END OF CLAIM LISTING THE REMAINDER OF THE PAGE HAS BEEN LEFT BLANK INTENTIONALLY
The device of claim -413, further comprising a subsidiary insulating layer between the base substrate and the gate electrode, wherein the substrate includes a semiconductor.
The device of claim -113, where in at least one of the first electrode and the second electrode is transparent or translucent.
An organic light emitting display, comprising: a switching unit including a graphene semiconductor device, wherein the switching unit has a first terminal, a second terminal, and a third terminal; a scanning li ne connected to the first terminal of the switching unit; a data line connected to the second terminal of the switching unit; and a li ght emitt in g unit connected to the third terminal of the switching unit, wherein the graphene semiconductor device in cludes, a gate electrode on a substrate, a gate insulat in g layer on the gate electrode, a graphene member on the gate insulating layer, a semiconductor member jo in ed with the graphene member, a first electrode on the semiconductor member, and a second electrode on the graphene member, wherein the second electrode is spaced apart from the semiconductor member and the first electrode. SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615504.3.1433.127.2193.184.svg 0.19 2.533 Graph Black and white Atty. Dkt. No. 15639-000075-US Page 6 of
An organic light emitting display, comp ri sing: a switching unit in cluding a graphene semiconductor device, wherein the switching unit includes a first terminal, a second terminal, and a third terminal; a scann m g line connected to the first terminal of the switching unit; a data line connected to the second terminal of the switching unit; a dr ivin g unit having a first terminal and a second terminal, wherein the first terminal of the driving u ni t is connected to the third terminal of the switching u nit; and a light emitting unit connected to the second terminal of the driving unit, wherein the graphene semiconductor device includes, a gate electrode on a substrate, a gate insulating layer on the gate electrode, a graphene member on the gate insulating layer, a semiconductor member joined with the graphene member, a first electrode on the semiconductor member, and a second electrode on the graphene member, wherein the second electrode is spaced apart from the semiconductor member and the first electrode.
A memory, comprising: a switching u ni t includ in g a graphene semiconductor device, wherein the switching unit includes a first terminal, a second terminal, and a third terminal; a word l in e connected to the first terminal of the switching u nit; a gate line connected to the second term in al of the switching unit; a resistive unit hav in g a first terminal and a second terminal, wherein the first terminal of the resistive unit is connected to the third terminal of the switching unit; and a bit line connected to the second terminal of the resistive unit, wherein the graphene semiconductor device includes, a gate electrode on a substrate, a gate insulating layer on the gate electrode, a graphene member on the gate insulating layer, a semiconductor member joined with the graphene member, a first electrode on the semiconductor member, and a second electrode on the graphene member, wherein the second electrode is spaced apart from the semiconductor member and the first electrode. U. S. Application No. 13/523,554 Atty. Dkt. No. 15639-000075-US Page 7 of
Layer stacks claimed or described, ordered top of device to substrate.
graphene semiconductor device (method)
graphene semiconductor device with light emitting layer
graphene semiconductor device with resistive material layer
organic light emitting display with graphene semiconductor switching unit
memory with graphene semiconductor switching unit
Materials described outside the worked examples.
graphene
sacrificial layer
semiconductor layer
silicon
Si
gallium arsenide
GaAs
indium phosphide
InP
gallium phosphide
GaP
indium arsenide
InAs
silicon dioxide
SiO₂
silicon nitride
SiN
aluminum oxide
Al₂O₃
hafnium dioxide
HfO₂
zirconium dioxide
ZrO₂
aluminum gallium arsenide
AlGaAs
aluminum arsenide
AlAs
light emitting layer
N-type semiconductor
resistive material layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a graph showing a current-voltage characteristic of the graphene thin film diode shown in
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE
P-GAN-DOWN MICRO-LED ON SEMI-POLAR ORIENTED GAN
SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS INCLUDING INDIUM GALLIUM NITRIDE, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND RELATED LIGHT EMITTING DEVICES
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 to 5 are schematic sectional views illustrating a method of manufacturing a graphene semiconductor device according to example embodiments. [0029]
FIG. 2, a transfer substrate 150 may be stuck to the multilayered member with an adhesive layer 160. In example embodiments, the transfer substrate 150 may be …
FIG. 3. Therefore, the first electrode 770 may serve as an anode of the switching diode, while the second electrode 780 may serve as a cathode of the switching …
FIG. 4, an insulating layer 220 may be deposited on a base substrate 210, and a graphene layer 230 may be then deposited on the insulating layer 220 to form …
FIG. 5, the two laminates 100 and 200 may be attached to each other such that the exposed surface of the semiconductor layer 130 in the process shown in
FIG. 6 is a schematic diagram of a graphene thin film diode according to example embodiments. [0030]
FIG. 7 is a graph showing a current-voltage characteristic of the graphene thin film diode shown in
FIGS. 8 to 12 are schematic sectional views illustrating a method of manufacturing a graphene thin film diode shown in
FIG. 9, portions of the conductor layer 440 and the semiconductor layer 430, which are left against (or, after) the etching, may become a first electrode 370 …
FIG. 10 contacts a surface of the graphene layer 355. In example embodiments, the gate electrode 330 may be aligned with the semiconductor member 360. [0093] …
FIG. 11, a subsidiary insulating layer 320 and a conductor layer (not shown) may be deposited in sequence on a base substrate 310. The subsidiary insulating …
FIG. 12, a laminate including the layers 360, 370, 460 and 450 shown in
FIG. 13 is a schematic diagram of a structure that forms at least a portion of a pixel in an OLED according to example embodiments. [0033]
FIG. 14 is a schematic diagram of another structure that forms at least a portion of a pixel in an OLED according to example embodiments. [0034]
FIG. 15 is a schematic diagram of a structure that forms at least a portion of a cell in an RRAM according to example embodiments. [0035]
FIG. 16 is a block diagram of a pixel of an OLED according to example embodiments. [0036]
FIG. 17 is an example equivalent circuit diagram of the pixel shown in
FIG. 18 is a block diagram of another pixel of an OLED according to example embodiments. [0038]
FIG. 19 is an example equivalent circuit diagram of the pixel shown in
FIG. 20 is a block diagram of a cell of a RRAM according to example embodiments. [0040]
FIG. 21 is an example equivalent circuit diagram of the cell shown in
FIG. 22 is a schematic layout view of an OLED according to example embodiments. [0042]
FIG. 23 is a schematically expanded layout view of a pixel of the OLED shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(ORIGINAL) A method of manufacturing a graphene semiconductor device, the method compris ing: forming a multilayered member inc lud in g a sacrificial substrate, a sac ri ficial layer, and a semiconductor layer deposited m sequence; forming a transfer substrate on the semiconductor layer; forming a first laminate including the transfer substrate and the semiconductor layer by removing the sacrificial layer to separate the sac n ficial substrate from the semiconductor layer; forming a second laminate by forming a graphene layer on a base substrate; combining the first laminate and the second laminate such that the semiconductor layer contacts the graphene layer; and remov in g the transfer substrate.
(ORIGINAL) The method of claim 1, wherein the semiconductor layer includes at least one of Si, GaAs, InP, GaP, and InAs.
(ORIGINAL) The method of claim 1, wherein the sacrificial layer includes at least one of SiO2, SiN, A 12O3, HfO 2, ZrO 2, A l GaAs, and A l As.
(ORIGINAL) The method of claim 1, wherein forming the multilayered member includes, depositing a conductor layer on the semiconductor layer; patterning the conductor layer to form a first electrode; and patterning the semiconductor layer to form a semiconductor member. U.S. App li cation No. 13/523,554 Atty. Dkt. No. 15639-000075-US Page 3 of 10 SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615501.7.463.347.2227.399.svg 0.173 5.88 Graph Black and white lam in ate and the second laminate includes contacting the semiconductor member with the graphene layer, and wherein the method further comprises forming a second electrode on an exposed surface of the graphene layer. SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615501.12.457.834.2224.884.svg 0.167 5.89 Graph Black and white lam in ate includes, forming a gate electrode on the base substrate; forming a gate insulating layer on the gate electrode and the base substrate; and forming the graphene layer on the gate insulating layer, and where in combining the first laminate and the second laminate includes aligning the gate electrode with the semiconductor member.
The method of claim 6, further comprising: forming a light emitting layer; and forming a third electrode on the light emitt in g layer, where in the light emitting layer is on the second electrode when the semiconductor layer includes an N-type semiconductor, and the light emitt in g layer is on the first electrode when the semiconductor layer includes a P-type semiconductor.
The method of claim 6, further comprising: form in g a resistive mate ri al layer and a third electrode on one of the first electrode and the second electrode, wherein the resistive material layer has a resistance that varies based on a voltage across ends of the resistive material layer.
(ORIGINAL) The method of claim 6, where in the base substrate in cludes an in sulator, and the gate electrode contacts the base substrate.
The method of claim 6, wherein the base substrate includes a semiconductor, and SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615502.2.1444.126.2202.183.svg 0.19 2.527 Graph Black and white Atty. Dkt. No. 15639-000075-US Page 4 of 10 forming the second laminate further includes form in g a subsidiary insulating layer between the base substrate and the gate electrode. original
. canceled
The device of claim 1413, wherein the semiconductor layer includes at least one of Si, GaAs, InP, GaP, and InAs.
A graphene semiconductor device, The-devee ofe laim11, further comprising: a gate electrode on a substrate; a gate insulat in g la y er on the gate electrode; a graphene member on the gate in sulat in g la yer; a semiconductor member oin ed with the graphene member; a first electrode on the semiconductor member; a second electrode on the graphene member; a light emitting layer on one of the first electrode and the second electrode; and a third electrode on the light emitting layer, wherein the second electrode is s p aced apart from the semiconductor member and the first electrode, the li ght emitting layer is on the second electrode when the semiconductor layer includes an N-type semiconductor, and the light emitting layer is on the first electrode when the semiconductor layer includes a P-type semiconductor.
A graphene sem i conductor device, T-he-4eviee ef elaim 1,further- comprising: a gate electrode on a substrate; a gate in sulat in g layer on the gate electrode; a graphene member on the gate insulat mn g la y er; a semiconductor member i oined with the graphene member; a first electrode on the semiconductor member; a second electrode on the graphene member; SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615503.5.1432.194.2194.291.svg 0.323 2.54 Graph Black and white U.S. Application No. 13/523,554 a resistive material layer on one of the first electrode and the second electrode; and a third electrode on the resistive material layer, where in the second electrode is spaced apart from the semiconductor member and the first electrode, and the resistive material layer has a resistance that varies based on a voltage across ends of the resistive material layer. SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615503.15.438.1078.2198.1128.svg 0.167 5.867 Chemistry Black and white substrate includes an insulator, and the gate electrode contacts the substrate.
(NE W) The device of claim 14, further comprising: a subsidiary insulating layer between the base substrate and the gate electrode, wherein the base substrate includes a semiconductor. END OF CLAIM LISTING THE REMAINDER OF THE PAGE HAS BEEN LEFT BLANK INTENTIONALLY
The device of claim -413, further comprising a subsidiary insulating layer between the base substrate and the gate electrode, wherein the substrate includes a semiconductor.
The device of claim -113, where in at least one of the first electrode and the second electrode is transparent or translucent.
An organic light emitting display, comprising: a switching unit including a graphene semiconductor device, wherein the switching unit has a first terminal, a second terminal, and a third terminal; a scanning li ne connected to the first terminal of the switching unit; a data line connected to the second terminal of the switching unit; and a li ght emitt in g unit connected to the third terminal of the switching unit, wherein the graphene semiconductor device in cludes, a gate electrode on a substrate, a gate insulat in g layer on the gate electrode, a graphene member on the gate insulating layer, a semiconductor member jo in ed with the graphene member, a first electrode on the semiconductor member, and a second electrode on the graphene member, wherein the second electrode is spaced apart from the semiconductor member and the first electrode. SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615504.3.1433.127.2193.184.svg 0.19 2.533 Graph Black and white Atty. Dkt. No. 15639-000075-US Page 6 of
An organic light emitting display, comp ri sing: a switching unit in cluding a graphene semiconductor device, wherein the switching unit includes a first terminal, a second terminal, and a third terminal; a scann m g line connected to the first terminal of the switching unit; a data line connected to the second terminal of the switching unit; a dr ivin g unit having a first terminal and a second terminal, wherein the first terminal of the driving u ni t is connected to the third terminal of the switching u nit; and a light emitting unit connected to the second terminal of the driving unit, wherein the graphene semiconductor device includes, a gate electrode on a substrate, a gate insulating layer on the gate electrode, a graphene member on the gate insulating layer, a semiconductor member joined with the graphene member, a first electrode on the semiconductor member, and a second electrode on the graphene member, wherein the second electrode is spaced apart from the semiconductor member and the first electrode.
A memory, comprising: a switching u ni t includ in g a graphene semiconductor device, wherein the switching unit includes a first terminal, a second terminal, and a third terminal; a word l in e connected to the first terminal of the switching u nit; a gate line connected to the second term in al of the switching unit; a resistive unit hav in g a first terminal and a second terminal, wherein the first terminal of the resistive unit is connected to the third terminal of the switching unit; and a bit line connected to the second terminal of the resistive unit, wherein the graphene semiconductor device includes, a gate electrode on a substrate, a gate insulating layer on the gate electrode, a graphene member on the gate insulating layer, a semiconductor member joined with the graphene member, a first electrode on the semiconductor member, and a second electrode on the graphene member, wherein the second electrode is spaced apart from the semiconductor member and the first electrode. U. S. Application No. 13/523,554 Atty. Dkt. No. 15639-000075-US Page 7 of
Layer stacks claimed or described, ordered top of device to substrate.
graphene semiconductor device (method)
graphene semiconductor device with light emitting layer
graphene semiconductor device with resistive material layer
organic light emitting display with graphene semiconductor switching unit
memory with graphene semiconductor switching unit
Materials described outside the worked examples.
graphene
sacrificial layer
semiconductor layer
silicon
Si
gallium arsenide
GaAs
indium phosphide
InP
gallium phosphide
GaP
indium arsenide
InAs
silicon dioxide
SiO₂
silicon nitride
SiN
aluminum oxide
Al₂O₃
hafnium dioxide
HfO₂
zirconium dioxide
ZrO₂
aluminum gallium arsenide
AlGaAs
aluminum arsenide
AlAs
light emitting layer
N-type semiconductor
resistive material layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a graph showing a current-voltage characteristic of the graphene thin film diode shown in
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE
P-GAN-DOWN MICRO-LED ON SEMI-POLAR ORIENTED GAN
SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS INCLUDING INDIUM GALLIUM NITRIDE, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND RELATED LIGHT EMITTING DEVICES
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 to 5 are schematic sectional views illustrating a method of manufacturing a graphene semiconductor device according to example embodiments. [0029]
FIG. 2, a transfer substrate 150 may be stuck to the multilayered member with an adhesive layer 160. In example embodiments, the transfer substrate 150 may be …
FIG. 3. Therefore, the first electrode 770 may serve as an anode of the switching diode, while the second electrode 780 may serve as a cathode of the switching …
FIG. 4, an insulating layer 220 may be deposited on a base substrate 210, and a graphene layer 230 may be then deposited on the insulating layer 220 to form …
FIG. 5, the two laminates 100 and 200 may be attached to each other such that the exposed surface of the semiconductor layer 130 in the process shown in
FIG. 6 is a schematic diagram of a graphene thin film diode according to example embodiments. [0030]
FIG. 7 is a graph showing a current-voltage characteristic of the graphene thin film diode shown in
FIGS. 8 to 12 are schematic sectional views illustrating a method of manufacturing a graphene thin film diode shown in
FIG. 9, portions of the conductor layer 440 and the semiconductor layer 430, which are left against (or, after) the etching, may become a first electrode 370 …
FIG. 10 contacts a surface of the graphene layer 355. In example embodiments, the gate electrode 330 may be aligned with the semiconductor member 360. [0093] …
FIG. 11, a subsidiary insulating layer 320 and a conductor layer (not shown) may be deposited in sequence on a base substrate 310. The subsidiary insulating …
FIG. 12, a laminate including the layers 360, 370, 460 and 450 shown in
FIG. 13 is a schematic diagram of a structure that forms at least a portion of a pixel in an OLED according to example embodiments. [0033]
FIG. 14 is a schematic diagram of another structure that forms at least a portion of a pixel in an OLED according to example embodiments. [0034]
FIG. 15 is a schematic diagram of a structure that forms at least a portion of a cell in an RRAM according to example embodiments. [0035]
FIG. 16 is a block diagram of a pixel of an OLED according to example embodiments. [0036]
FIG. 17 is an example equivalent circuit diagram of the pixel shown in
FIG. 18 is a block diagram of another pixel of an OLED according to example embodiments. [0038]
FIG. 19 is an example equivalent circuit diagram of the pixel shown in
FIG. 20 is a block diagram of a cell of a RRAM according to example embodiments. [0040]
FIG. 21 is an example equivalent circuit diagram of the cell shown in
FIG. 22 is a schematic layout view of an OLED according to example embodiments. [0042]
FIG. 23 is a schematically expanded layout view of a pixel of the OLED shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(ORIGINAL) A method of manufacturing a graphene semiconductor device, the method compris ing: forming a multilayered member inc lud in g a sacrificial substrate, a sac ri ficial layer, and a semiconductor layer deposited m sequence; forming a transfer substrate on the semiconductor layer; forming a first laminate including the transfer substrate and the semiconductor layer by removing the sacrificial layer to separate the sac n ficial substrate from the semiconductor layer; forming a second laminate by forming a graphene layer on a base substrate; combining the first laminate and the second laminate such that the semiconductor layer contacts the graphene layer; and remov in g the transfer substrate.
(ORIGINAL) The method of claim 1, wherein the semiconductor layer includes at least one of Si, GaAs, InP, GaP, and InAs.
(ORIGINAL) The method of claim 1, wherein the sacrificial layer includes at least one of SiO2, SiN, A 12O3, HfO 2, ZrO 2, A l GaAs, and A l As.
(ORIGINAL) The method of claim 1, wherein forming the multilayered member includes, depositing a conductor layer on the semiconductor layer; patterning the conductor layer to form a first electrode; and patterning the semiconductor layer to form a semiconductor member. U.S. App li cation No. 13/523,554 Atty. Dkt. No. 15639-000075-US Page 3 of 10 SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615501.7.463.347.2227.399.svg 0.173 5.88 Graph Black and white lam in ate and the second laminate includes contacting the semiconductor member with the graphene layer, and wherein the method further comprises forming a second electrode on an exposed surface of the graphene layer. SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615501.12.457.834.2224.884.svg 0.167 5.89 Graph Black and white lam in ate includes, forming a gate electrode on the base substrate; forming a gate insulating layer on the gate electrode and the base substrate; and forming the graphene layer on the gate insulating layer, and where in combining the first laminate and the second laminate includes aligning the gate electrode with the semiconductor member.
The method of claim 6, further comprising: forming a light emitting layer; and forming a third electrode on the light emitt in g layer, where in the light emitting layer is on the second electrode when the semiconductor layer includes an N-type semiconductor, and the light emitt in g layer is on the first electrode when the semiconductor layer includes a P-type semiconductor.
The method of claim 6, further comprising: form in g a resistive mate ri al layer and a third electrode on one of the first electrode and the second electrode, wherein the resistive material layer has a resistance that varies based on a voltage across ends of the resistive material layer.
(ORIGINAL) The method of claim 6, where in the base substrate in cludes an in sulator, and the gate electrode contacts the base substrate.
The method of claim 6, wherein the base substrate includes a semiconductor, and SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615502.2.1444.126.2202.183.svg 0.19 2.527 Graph Black and white Atty. Dkt. No. 15639-000075-US Page 4 of 10 forming the second laminate further includes form in g a subsidiary insulating layer between the base substrate and the gate electrode. original
. canceled
The device of claim 1413, wherein the semiconductor layer includes at least one of Si, GaAs, InP, GaP, and InAs.
A graphene semiconductor device, The-devee ofe laim11, further comprising: a gate electrode on a substrate; a gate insulat in g la y er on the gate electrode; a graphene member on the gate in sulat in g la yer; a semiconductor member oin ed with the graphene member; a first electrode on the semiconductor member; a second electrode on the graphene member; a light emitting layer on one of the first electrode and the second electrode; and a third electrode on the light emitting layer, wherein the second electrode is s p aced apart from the semiconductor member and the first electrode, the li ght emitting layer is on the second electrode when the semiconductor layer includes an N-type semiconductor, and the light emitting layer is on the first electrode when the semiconductor layer includes a P-type semiconductor.
A graphene sem i conductor device, T-he-4eviee ef elaim 1,further- comprising: a gate electrode on a substrate; a gate in sulat in g layer on the gate electrode; a graphene member on the gate insulat mn g la y er; a semiconductor member i oined with the graphene member; a first electrode on the semiconductor member; a second electrode on the graphene member; SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615503.5.1432.194.2194.291.svg 0.323 2.54 Graph Black and white U.S. Application No. 13/523,554 a resistive material layer on one of the first electrode and the second electrode; and a third electrode on the resistive material layer, where in the second electrode is spaced apart from the semiconductor member and the first electrode, and the resistive material layer has a resistance that varies based on a voltage across ends of the resistive material layer. SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615503.15.438.1078.2198.1128.svg 0.167 5.867 Chemistry Black and white substrate includes an insulator, and the gate electrode contacts the substrate.
(NE W) The device of claim 14, further comprising: a subsidiary insulating layer between the base substrate and the gate electrode, wherein the base substrate includes a semiconductor. END OF CLAIM LISTING THE REMAINDER OF THE PAGE HAS BEEN LEFT BLANK INTENTIONALLY
The device of claim -413, further comprising a subsidiary insulating layer between the base substrate and the gate electrode, wherein the substrate includes a semiconductor.
The device of claim -113, where in at least one of the first electrode and the second electrode is transparent or translucent.
An organic light emitting display, comprising: a switching unit including a graphene semiconductor device, wherein the switching unit has a first terminal, a second terminal, and a third terminal; a scanning li ne connected to the first terminal of the switching unit; a data line connected to the second terminal of the switching unit; and a li ght emitt in g unit connected to the third terminal of the switching unit, wherein the graphene semiconductor device in cludes, a gate electrode on a substrate, a gate insulat in g layer on the gate electrode, a graphene member on the gate insulating layer, a semiconductor member jo in ed with the graphene member, a first electrode on the semiconductor member, and a second electrode on the graphene member, wherein the second electrode is spaced apart from the semiconductor member and the first electrode. SVG 13523554.11-19-2013.HOFUAYVQPXXIFW4.CLM7615504.3.1433.127.2193.184.svg 0.19 2.533 Graph Black and white Atty. Dkt. No. 15639-000075-US Page 6 of
An organic light emitting display, comp ri sing: a switching unit in cluding a graphene semiconductor device, wherein the switching unit includes a first terminal, a second terminal, and a third terminal; a scann m g line connected to the first terminal of the switching unit; a data line connected to the second terminal of the switching unit; a dr ivin g unit having a first terminal and a second terminal, wherein the first terminal of the driving u ni t is connected to the third terminal of the switching u nit; and a light emitting unit connected to the second terminal of the driving unit, wherein the graphene semiconductor device includes, a gate electrode on a substrate, a gate insulating layer on the gate electrode, a graphene member on the gate insulating layer, a semiconductor member joined with the graphene member, a first electrode on the semiconductor member, and a second electrode on the graphene member, wherein the second electrode is spaced apart from the semiconductor member and the first electrode.
A memory, comprising: a switching u ni t includ in g a graphene semiconductor device, wherein the switching unit includes a first terminal, a second terminal, and a third terminal; a word l in e connected to the first terminal of the switching u nit; a gate line connected to the second term in al of the switching unit; a resistive unit hav in g a first terminal and a second terminal, wherein the first terminal of the resistive unit is connected to the third terminal of the switching unit; and a bit line connected to the second terminal of the resistive unit, wherein the graphene semiconductor device includes, a gate electrode on a substrate, a gate insulating layer on the gate electrode, a graphene member on the gate insulating layer, a semiconductor member joined with the graphene member, a first electrode on the semiconductor member, and a second electrode on the graphene member, wherein the second electrode is spaced apart from the semiconductor member and the first electrode. U. S. Application No. 13/523,554 Atty. Dkt. No. 15639-000075-US Page 7 of
Layer stacks claimed or described, ordered top of device to substrate.
graphene semiconductor device (method)
graphene semiconductor device with light emitting layer
graphene semiconductor device with resistive material layer
organic light emitting display with graphene semiconductor switching unit
memory with graphene semiconductor switching unit
Materials described outside the worked examples.
graphene
sacrificial layer
semiconductor layer
silicon
Si
gallium arsenide
GaAs
indium phosphide
InP
gallium phosphide
GaP
indium arsenide
InAs
silicon dioxide
SiO₂
silicon nitride
SiN
aluminum oxide
Al₂O₃
hafnium dioxide
HfO₂
zirconium dioxide
ZrO₂
aluminum gallium arsenide
AlGaAs
aluminum arsenide
AlAs
light emitting layer
N-type semiconductor
resistive material layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a graph showing a current-voltage characteristic of the graphene thin film diode shown in
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE
P-GAN-DOWN MICRO-LED ON SEMI-POLAR ORIENTED GAN
SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS INCLUDING INDIUM GALLIUM NITRIDE, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND RELATED LIGHT EMITTING DEVICES