The GaN switching device of claim 1, wherein the pull-down driver transistor is distributed as a plurality of pull-down driver transistor elements, each pull-down driver transistor element being arranged for driving a respective section of the GaN power transistor and wherein a single pull-up driver transistor is provided for driving all sections 15 of the GaN power transistor.

The GaN switching device of claim 1, wherein both the pull-up driver transistor and pull-down driver transistor are distributed as a plurality of distributed driver elements, each driver element comprising an individual pull-down driver transistor and an individual pull-up driver transistor in series and providing a gate output for driving its respective 20 section of the GaN power transistor.

The GaN switching device of claim 1, wherein the plurality of sections of the GaN FET and the plurality of driver elements are arranged to provide a layout wherein each one of the distributed driver elements is placed in close physical proximity to the respective one of the sections of the large GaN FET that it drives.

The GaN switching device of claim 1, wherein each one of the driver elements is placed in close physical proximity to the respective one of the sections of the large GaN power switch, and wherein routing and sizing of respective interconnect tracks connecting the distributed driver elements and respective sections of GaN switch are selected to minimize loop inductance. 19

The device of claim 1, wherein the gate output track connection of the driver element which drives a section of the gate of the large GaN power switch and the return track connection to the source of the pull-down driver transistor of the driver element are magnetically mirrored so as to reduce the loop inductance.

The device of claim 1, wherein the routing and sizing of interconnect tracks for the gate output and return between each driver element and respective sections of the GaN power switch are arranged to reduce the loop inductance.

A GaN switching device according to claim 10, wherein each driver element comprises 25 a first, pull-up E-Mode GaN driver transistor D 1 and a second, pull-down E-Mode GaN driver transistor D2; 20 the drain of D 1 being coupled to V c c, and the source of D 1 being coupled to the drain of D₂ at node N, which is coupled to the gate of the respective section of D3, and an internal source-sense connection closely coupling the source of the respective section of D₃ and the source of D2, such that the first transistor D 1 delivers a drive voltage to the gate of the respective section of the GaN transistor switch D3, and the second transistor D₂ clamps the gate of the respective section the GaN transistor switch D₃ by means of the internal source-sense connection SS ntemi; inputs for coupling to a pre-driver supplying gate drive voltages to the gates of D₁ and D₂ of each driver element and optionally to the gates of each section of D3, and 10 an external source-sense connection SS exteai for coupling to the pre-driver.

The device of claim 10, wherein each section D₃ n of D₃ has a respective individual driver element comprising a pull-up driver element D lIn and a pull-down driver element D2n.

The device of claim 10, wherein each section D₃ n of D₃ is coupled to a respective individual pull-down driver element D ln, and wherein a single pull-up driver element D₂ is coupled to the plurality of sections of D3.

The GaN switching device of claim 1, wherein the pull-down driver transistor is distributed as a plurality of pull-down driver transistor elements, each pull-down driver transistor element being arranged for driving a respective section of the GaN power transistor and wherein a single pull-up driver transistor is provided for driving all sections 15 of the GaN power transistor.

The GaN switching device of claim 1, wherein both the pull-up driver transistor and pull-down driver transistor are distributed as a plurality of distributed driver elements, each driver element comprising an individual pull-down driver transistor and an individual pull-up driver transistor in series and providing a gate output for driving its respective 20 section of the GaN power transistor.

The GaN switching device of claim 1, wherein the plurality of sections of the GaN FET and the plurality of driver elements are arranged to provide a layout wherein each one of the distributed driver elements is placed in close physical proximity to the respective one of the sections of the large GaN FET that it drives.

The GaN switching device of claim 1, wherein each one of the driver elements is placed in close physical proximity to the respective one of the sections of the large GaN power switch, and wherein routing and sizing of respective interconnect tracks connecting the distributed driver elements and respective sections of GaN switch are selected to minimize loop inductance. 19

The device of claim 1, wherein the gate output track connection of the driver element which drives a section of the gate of the large GaN power switch and the return track connection to the source of the pull-down driver transistor of the driver element are magnetically mirrored so as to reduce the loop inductance.

The device of claim 1, wherein the routing and sizing of interconnect tracks for the gate output and return between each driver element and respective sections of the GaN power switch are arranged to reduce the loop inductance.

A GaN switching device according to claim 10, wherein each driver element comprises 25 a first, pull-up E-Mode GaN driver transistor D 1 and a second, pull-down E-Mode GaN driver transistor D2; 20 the drain of D 1 being coupled to V c c, and the source of D 1 being coupled to the drain of D₂ at node N, which is coupled to the gate of the respective section of D3, and an internal source-sense connection closely coupling the source of the respective section of D₃ and the source of D2, such that the first transistor D 1 delivers a drive voltage to the gate of the respective section of the GaN transistor switch D3, and the second transistor D₂ clamps the gate of the respective section the GaN transistor switch D₃ by means of the internal source-sense connection SS ntemi; inputs for coupling to a pre-driver supplying gate drive voltages to the gates of D₁ and D₂ of each driver element and optionally to the gates of each section of D3, and 10 an external source-sense connection SS exteai for coupling to the pre-driver.

The device of claim 10, wherein each section D₃ n of D₃ has a respective individual driver element comprising a pull-up driver element D lIn and a pull-down driver element D2n.

The device of claim 10, wherein each section D₃ n of D₃ is coupled to a respective individual pull-down driver element D ln, and wherein a single pull-up driver element D₂ is coupled to the plurality of sections of D3.

The GaN switching device of claim 1, wherein the pull-down driver transistor is distributed as a plurality of pull-down driver transistor elements, each pull-down driver transistor element being arranged for driving a respective section of the GaN power transistor and wherein a single pull-up driver transistor is provided for driving all sections 15 of the GaN power transistor.

The GaN switching device of claim 1, wherein both the pull-up driver transistor and pull-down driver transistor are distributed as a plurality of distributed driver elements, each driver element comprising an individual pull-down driver transistor and an individual pull-up driver transistor in series and providing a gate output for driving its respective 20 section of the GaN power transistor.

The GaN switching device of claim 1, wherein the plurality of sections of the GaN FET and the plurality of driver elements are arranged to provide a layout wherein each one of the distributed driver elements is placed in close physical proximity to the respective one of the sections of the large GaN FET that it drives.

The GaN switching device of claim 1, wherein each one of the driver elements is placed in close physical proximity to the respective one of the sections of the large GaN power switch, and wherein routing and sizing of respective interconnect tracks connecting the distributed driver elements and respective sections of GaN switch are selected to minimize loop inductance. 19

The device of claim 1, wherein the gate output track connection of the driver element which drives a section of the gate of the large GaN power switch and the return track connection to the source of the pull-down driver transistor of the driver element are magnetically mirrored so as to reduce the loop inductance.

The device of claim 1, wherein the routing and sizing of interconnect tracks for the gate output and return between each driver element and respective sections of the GaN power switch are arranged to reduce the loop inductance.

A GaN switching device according to claim 10, wherein each driver element comprises 25 a first, pull-up E-Mode GaN driver transistor D 1 and a second, pull-down E-Mode GaN driver transistor D2; 20 the drain of D 1 being coupled to V c c, and the source of D 1 being coupled to the drain of D₂ at node N, which is coupled to the gate of the respective section of D3, and an internal source-sense connection closely coupling the source of the respective section of D₃ and the source of D2, such that the first transistor D 1 delivers a drive voltage to the gate of the respective section of the GaN transistor switch D3, and the second transistor D₂ clamps the gate of the respective section the GaN transistor switch D₃ by means of the internal source-sense connection SS ntemi; inputs for coupling to a pre-driver supplying gate drive voltages to the gates of D₁ and D₂ of each driver element and optionally to the gates of each section of D3, and 10 an external source-sense connection SS exteai for coupling to the pre-driver.

The device of claim 10, wherein each section D₃ n of D₃ has a respective individual driver element comprising a pull-up driver element D lIn and a pull-down driver element D2n.

The device of claim 10, wherein each section D₃ n of D₃ is coupled to a respective individual pull-down driver element D ln, and wherein a single pull-up driver element D₂ is coupled to the plurality of sections of D3.

The GaN switching device of claim 1, wherein the pull-down driver transistor is distributed as a plurality of pull-down driver transistor elements, each pull-down driver transistor element being arranged for driving a respective section of the GaN power transistor and wherein a single pull-up driver transistor is provided for driving all sections 15 of the GaN power transistor.

The GaN switching device of claim 1, wherein both the pull-up driver transistor and pull-down driver transistor are distributed as a plurality of distributed driver elements, each driver element comprising an individual pull-down driver transistor and an individual pull-up driver transistor in series and providing a gate output for driving its respective 20 section of the GaN power transistor.

The GaN switching device of claim 1, wherein the plurality of sections of the GaN FET and the plurality of driver elements are arranged to provide a layout wherein each one of the distributed driver elements is placed in close physical proximity to the respective one of the sections of the large GaN FET that it drives.

The GaN switching device of claim 1, wherein each one of the driver elements is placed in close physical proximity to the respective one of the sections of the large GaN power switch, and wherein routing and sizing of respective interconnect tracks connecting the distributed driver elements and respective sections of GaN switch are selected to minimize loop inductance. 19

The device of claim 1, wherein the gate output track connection of the driver element which drives a section of the gate of the large GaN power switch and the return track connection to the source of the pull-down driver transistor of the driver element are magnetically mirrored so as to reduce the loop inductance.

The device of claim 1, wherein the routing and sizing of interconnect tracks for the gate output and return between each driver element and respective sections of the GaN power switch are arranged to reduce the loop inductance.

A GaN switching device according to claim 10, wherein each driver element comprises 25 a first, pull-up E-Mode GaN driver transistor D 1 and a second, pull-down E-Mode GaN driver transistor D2; 20 the drain of D 1 being coupled to V c c, and the source of D 1 being coupled to the drain of D₂ at node N, which is coupled to the gate of the respective section of D3, and an internal source-sense connection closely coupling the source of the respective section of D₃ and the source of D2, such that the first transistor D 1 delivers a drive voltage to the gate of the respective section of the GaN transistor switch D3, and the second transistor D₂ clamps the gate of the respective section the GaN transistor switch D₃ by means of the internal source-sense connection SS ntemi; inputs for coupling to a pre-driver supplying gate drive voltages to the gates of D₁ and D₂ of each driver element and optionally to the gates of each section of D3, and 10 an external source-sense connection SS exteai for coupling to the pre-driver.

The device of claim 10, wherein each section D₃ n of D₃ has a respective individual driver element comprising a pull-up driver element D lIn and a pull-down driver element D2n.

The device of claim 10, wherein each section D₃ n of D₃ is coupled to a respective individual pull-down driver element D ln, and wherein a single pull-up driver element D₂ is coupled to the plurality of sections of D3.