A method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method comprising: ldentifying identif yinq, by a computing device, a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements that comprise transistors formed with a non-graphene semiconductor material and are configured to receive signals from at least one combinatorial element included in an immediately preceding level of the IC design, at least one sequential element, or a combination of both; selecting, by the computing device, one of the plurality of levels associated with the IC design; replacing, by the computing device, combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining, by the computing device, an energy leakage rate associated with the first configuration; determining, by the computing device, a time delay associated with the first configuration; comparing, by the computing device, the determined time delay to a target time delay for the IC design and the determined energy leakage rate to a target energy leakage rate for the IC design; and in response to the determined energy leakage rate being less than the target energy leakage rate while the determined time delay meets the target time delay, selecting, by the computing device, another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration, Page 8 PATENT Atty Dkt No 121-0036-US-NAT wherein each of the combinatorial elements that comprise transistors formed with graphene has a shorter time delay and a greater energy leakage rate than the respective combinatorial element being replaced.

A method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method comprising: identifying, by a computing device, a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements that comprise transistors formed with a non-graphene semiconductor material and are configured to receive signals from at least one combinatorial element included in an immediately preceding level of the IC design, at least one sequential element, or a combination of both; selecting, by the computing device, one of the plurality of levels associated with the IC design; replacing, by the computing device, combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining, by the computing device, an energy leakage rate associated with the first configuration; determining, by the computing device, a time delay associated with the first configuration; comparing, by the computing device, the determined time delay to a target time delay for the IC design and the determined energy leakage rate to a target energy leakage rate for the IC design; and in response to the determined time delay being greater than the target time delay while the determined energy leakage rate meets the target energy leakage Page 10 PATENT Atty Dkt No 121-0036-US-NAT rate, selecting, by the computing device, another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration.

An article of manufacture, comprising: a non-transitory computer-readable medium having computer-executable instructions that, in response to execution by a processor, cause the processor to perform a method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method including: identifying a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements; selecting one of the plurality of levels associated with the IC design; replacing combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining a performance parameter of the IC design having the first configuration; comparing the determined performance parameter to a target performance parameter for the IC design; and as a result of the comparing indicating that the target performance parameter permits a further change to the performance parameter of the IC design, selecting another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration. Page 12 PATENT Atty Dkt No 121-0036-US-NAT

A method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method comprising: ldentifying identif yinq, by a computing device, a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements that comprise transistors formed with a non-graphene semiconductor material and are configured to receive signals from at least one combinatorial element included in an immediately preceding level of the IC design, at least one sequential element, or a combination of both; selecting, by the computing device, one of the plurality of levels associated with the IC design; replacing, by the computing device, combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining, by the computing device, an energy leakage rate associated with the first configuration; determining, by the computing device, a time delay associated with the first configuration; comparing, by the computing device, the determined time delay to a target time delay for the IC design and the determined energy leakage rate to a target energy leakage rate for the IC design; and in response to the determined energy leakage rate being less than the target energy leakage rate while the determined time delay meets the target time delay, selecting, by the computing device, another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration, Page 8 PATENT Atty Dkt No 121-0036-US-NAT wherein each of the combinatorial elements that comprise transistors formed with graphene has a shorter time delay and a greater energy leakage rate than the respective combinatorial element being replaced.

A method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method comprising: identifying, by a computing device, a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements that comprise transistors formed with a non-graphene semiconductor material and are configured to receive signals from at least one combinatorial element included in an immediately preceding level of the IC design, at least one sequential element, or a combination of both; selecting, by the computing device, one of the plurality of levels associated with the IC design; replacing, by the computing device, combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining, by the computing device, an energy leakage rate associated with the first configuration; determining, by the computing device, a time delay associated with the first configuration; comparing, by the computing device, the determined time delay to a target time delay for the IC design and the determined energy leakage rate to a target energy leakage rate for the IC design; and in response to the determined time delay being greater than the target time delay while the determined energy leakage rate meets the target energy leakage Page 10 PATENT Atty Dkt No 121-0036-US-NAT rate, selecting, by the computing device, another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration.

An article of manufacture, comprising: a non-transitory computer-readable medium having computer-executable instructions that, in response to execution by a processor, cause the processor to perform a method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method including: identifying a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements; selecting one of the plurality of levels associated with the IC design; replacing combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining a performance parameter of the IC design having the first configuration; comparing the determined performance parameter to a target performance parameter for the IC design; and as a result of the comparing indicating that the target performance parameter permits a further change to the performance parameter of the IC design, selecting another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration. Page 12 PATENT Atty Dkt No 121-0036-US-NAT

A method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method comprising: ldentifying identif yinq, by a computing device, a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements that comprise transistors formed with a non-graphene semiconductor material and are configured to receive signals from at least one combinatorial element included in an immediately preceding level of the IC design, at least one sequential element, or a combination of both; selecting, by the computing device, one of the plurality of levels associated with the IC design; replacing, by the computing device, combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining, by the computing device, an energy leakage rate associated with the first configuration; determining, by the computing device, a time delay associated with the first configuration; comparing, by the computing device, the determined time delay to a target time delay for the IC design and the determined energy leakage rate to a target energy leakage rate for the IC design; and in response to the determined energy leakage rate being less than the target energy leakage rate while the determined time delay meets the target time delay, selecting, by the computing device, another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration, Page 8 PATENT Atty Dkt No 121-0036-US-NAT wherein each of the combinatorial elements that comprise transistors formed with graphene has a shorter time delay and a greater energy leakage rate than the respective combinatorial element being replaced.

A method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method comprising: identifying, by a computing device, a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements that comprise transistors formed with a non-graphene semiconductor material and are configured to receive signals from at least one combinatorial element included in an immediately preceding level of the IC design, at least one sequential element, or a combination of both; selecting, by the computing device, one of the plurality of levels associated with the IC design; replacing, by the computing device, combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining, by the computing device, an energy leakage rate associated with the first configuration; determining, by the computing device, a time delay associated with the first configuration; comparing, by the computing device, the determined time delay to a target time delay for the IC design and the determined energy leakage rate to a target energy leakage rate for the IC design; and in response to the determined time delay being greater than the target time delay while the determined energy leakage rate meets the target energy leakage Page 10 PATENT Atty Dkt No 121-0036-US-NAT rate, selecting, by the computing device, another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration.

An article of manufacture, comprising: a non-transitory computer-readable medium having computer-executable instructions that, in response to execution by a processor, cause the processor to perform a method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method including: identifying a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements; selecting one of the plurality of levels associated with the IC design; replacing combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining a performance parameter of the IC design having the first configuration; comparing the determined performance parameter to a target performance parameter for the IC design; and as a result of the comparing indicating that the target performance parameter permits a further change to the performance parameter of the IC design, selecting another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration. Page 12 PATENT Atty Dkt No 121-0036-US-NAT

A method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method comprising: ldentifying identif yinq, by a computing device, a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements that comprise transistors formed with a non-graphene semiconductor material and are configured to receive signals from at least one combinatorial element included in an immediately preceding level of the IC design, at least one sequential element, or a combination of both; selecting, by the computing device, one of the plurality of levels associated with the IC design; replacing, by the computing device, combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining, by the computing device, an energy leakage rate associated with the first configuration; determining, by the computing device, a time delay associated with the first configuration; comparing, by the computing device, the determined time delay to a target time delay for the IC design and the determined energy leakage rate to a target energy leakage rate for the IC design; and in response to the determined energy leakage rate being less than the target energy leakage rate while the determined time delay meets the target time delay, selecting, by the computing device, another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration, Page 8 PATENT Atty Dkt No 121-0036-US-NAT wherein each of the combinatorial elements that comprise transistors formed with graphene has a shorter time delay and a greater energy leakage rate than the respective combinatorial element being replaced.

A method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method comprising: identifying, by a computing device, a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements that comprise transistors formed with a non-graphene semiconductor material and are configured to receive signals from at least one combinatorial element included in an immediately preceding level of the IC design, at least one sequential element, or a combination of both; selecting, by the computing device, one of the plurality of levels associated with the IC design; replacing, by the computing device, combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining, by the computing device, an energy leakage rate associated with the first configuration; determining, by the computing device, a time delay associated with the first configuration; comparing, by the computing device, the determined time delay to a target time delay for the IC design and the determined energy leakage rate to a target energy leakage rate for the IC design; and in response to the determined time delay being greater than the target time delay while the determined energy leakage rate meets the target energy leakage Page 10 PATENT Atty Dkt No 121-0036-US-NAT rate, selecting, by the computing device, another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration.

An article of manufacture, comprising: a non-transitory computer-readable medium having computer-executable instructions that, in response to execution by a processor, cause the processor to perform a method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method including: identifying a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements; selecting one of the plurality of levels associated with the IC design; replacing combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining a performance parameter of the IC design having the first configuration; comparing the determined performance parameter to a target performance parameter for the IC design; and as a result of the comparing indicating that the target performance parameter permits a further change to the performance parameter of the IC design, selecting another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration. Page 12 PATENT Atty Dkt No 121-0036-US-NAT