Patent
US 8,569,089Patent
Atlas literature
Patent
US 8,569,089Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a 3-D perspective view of a semiconductor nano-device, according to an aspect of the invention. In general, a semiconductor nano-device 100 comprises …
FIGS. 2A, 2 B, 2C, 2 D, 2E, 2F, 2G, 2H, 2 1, 2J, 2K, 2L, 2M, 2N, 20 and 2P schematically illustrate a method for constructing a semiconductor nano-device at …
FIG. 20 after mounting an elongated nano- structure 170 on a surface of the graphene membrane 130 between the upper and lower open cavities 155 and 125. As …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
\nonie' Docket No \ (t1(2 7;i 104 2m T he li sti ng of t he Caim:. (O riginal) A method of i;n ting a. sen andfctor dce iL comprising: f1 n n i a bottom uate electrode in a substra te: in nun1112 a 114 insulat ing lax i over the \:t iaIe covering the bo ttom ode electrode; c illn a f i cavity m the first ins ulati ng la yer, wherein the first cavity is aligned with the bottom gate electrode; ti1 b, the first cavity with a second la y er of in %.n: in m ateria l: pl anar izin g t he second 1:n e t of insulatin g material using the first insulting layer as a n etch stop to fhnun a u t phln:rued ales fl, f miniig a um aphene lay er o n t h e first pl anai ied surface; linn in one or more sense electrodes on th e uraphenc L e, wherein the one or m11orle sense electrodes are disposed o n the g rap h ene l a e t adjaceni to the ini cavity; VoinL a third insulating la er over (lie 2iaphene la s ct and covering dle one or more sense electrodes; etchin g a second cavity in the thi d insuMinc la,,er. w herein the second cavity is ali g ned with the first cavity; filli n g the second cavity with a froua lh layer o f insulamino material; plaim zing the wounh layer o f insulatin g material -t'lpinC o n t he thirl insiln' lay er to fo-r a se cond pluiiiz ed surfacc: 1(m113 i a fit l insulating la y er o ver t h e second pla n arized surface, Corii iin' a top gate elccv'de over the f ifth in sulat i ng laxci. the top gate e lect rode aliied x ith the first and second cavities; dit in ' the substrate to form an individual se m ico n ducto r n u- im ucture; removing the second and fourth layers o f ins ula iin material from the first and second cav i ties, es-pcclix ely, to fo rm fi rst and second op eni. cavit i es, and mieinnlri an elongated nano-structure to a portion of the p aI phene layer that is snpciidc betwee n iw fi, and second open cavities. 2 \nimLe Docket No, \ (R (L)II 104731 S₂
(O rig inal) The me thod of claim, wherein forming the bottom gate electrode comprises fortmi ng a doped r egion in a semiconductor substrate, wherein the dope d i og ion serves a s the bott om gate electrode, 3, (Origi nal) The method o f claim 1, where in the elo n gated na no- struc tu re is a nano-li i e strcture.
(O riginal) The method of claim 1, wherein the L n Lid ted nano-st ruc ture is a nano- ill oh e structure.
(Or1i ia1) The nehod of claim 1, w herein t he elongated nano-st ruc ture is for med of s1 icon.
(Ori inal) The met ho d o f c lai m 1 wherein the elon g ated nano-stru c ture is for med of a metallic material. 7 (Origin al) T he method of claim 1, wh erei n the elongated nano-strctu re i s form ci of a carb on nanotube structure. 8 (O rigin al) The mcihod of claim 1, wherein foinuijg a grphene layer comprises tuan di rang a graphen e f ilm from a su bstrate upon k hich the ? saphcne film is grown.
9. (C utiemdn0 Amended) A method of.mit111 a semiconductor device>,,E nipri i an' tonngul a bottom ate elect rode; Ca ming a first iin1ulat la yer over the bottom g ate e l ectr od e, ithe f irs t is l.ai nn layer com prising a first open cavity etched in a surface of the first i nsu lat ing lay er. wherein the first open c avi ty is;ali ned u i the botto m g ate e lec trode; f'iia ag a cn rllahe layer over an d in contact with said surf a ce of the first insu l ating l ayer; 1it Docket No \ (tlu2i 1043 2 fniing one or more sense electrodes on the uia phcne layer; Cun ingQ a seco nd ins ulai Eno layer o ver.iid in Coit ict u\ ith the ra phenblii Li the second insulati ng layer %orn pi ii a second open ca vity etched in the en 'iI ''lui I: ek ni herin 11:. 1t1E₁ t. i 'it [oh i nd ii ii " 11 the di, f.j g ca iy.......... '........}.!.... !."..i......i..l........d...h.h E r p n av t fan n m a top gate electrode over the sec ond insulat ing laver, wherein the top g ate elecio de is oli;e d with the first and second ope n cavit ies; nid Tounting an eltOntcd ni aini- tructure to a portion of 111 aphr' layer th at is; \uspeinded between the first and second open cavities.
(Oriinal) The method of claim 9. wh erein t he elongated nan o- structure is a nano- kni f e s tru cture,
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor nano-device with suspended graphene membrane
Materials described outside the worked examples.
graphene
insulating material
Patent
Atlas literature
Patent
US 8,569,089Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a 3-D perspective view of a semiconductor nano-device, according to an aspect of the invention. In general, a semiconductor nano-device 100 comprises …
FIGS. 2A, 2 B, 2C, 2 D, 2E, 2F, 2G, 2H, 2 1, 2J, 2K, 2L, 2M, 2N, 20 and 2P schematically illustrate a method for constructing a semiconductor nano-device at …
FIG. 20 after mounting an elongated nano- structure 170 on a surface of the graphene membrane 130 between the upper and lower open cavities 155 and 125. As …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
\nonie' Docket No \ (t1(2 7;i 104 2m T he li sti ng of t he Caim:. (O riginal) A method of i;n ting a. sen andfctor dce iL comprising: f1 n n i a bottom uate electrode in a substra te: in nun1112 a 114 insulat ing lax i over the \:t iaIe covering the bo ttom ode electrode; c illn a f i cavity m the first ins ulati ng la yer, wherein the first cavity is aligned with the bottom gate electrode; ti1 b, the first cavity with a second la y er of in %.n: in m ateria l: pl anar izin g t he second 1:n e t of insulatin g material using the first insulting layer as a n etch stop to fhnun a u t phln:rued ales fl, f miniig a um aphene lay er o n t h e first pl anai ied surface; linn in one or more sense electrodes on th e uraphenc L e, wherein the one or m11orle sense electrodes are disposed o n the g rap h ene l a e t adjaceni to the ini cavity; VoinL a third insulating la er over (lie 2iaphene la s ct and covering dle one or more sense electrodes; etchin g a second cavity in the thi d insuMinc la,,er. w herein the second cavity is ali g ned with the first cavity; filli n g the second cavity with a froua lh layer o f insulamino material; plaim zing the wounh layer o f insulatin g material -t'lpinC o n t he thirl insiln' lay er to fo-r a se cond pluiiiz ed surfacc: 1(m113 i a fit l insulating la y er o ver t h e second pla n arized surface, Corii iin' a top gate elccv'de over the f ifth in sulat i ng laxci. the top gate e lect rode aliied x ith the first and second cavities; dit in ' the substrate to form an individual se m ico n ducto r n u- im ucture; removing the second and fourth layers o f ins ula iin material from the first and second cav i ties, es-pcclix ely, to fo rm fi rst and second op eni. cavit i es, and mieinnlri an elongated nano-structure to a portion of the p aI phene layer that is snpciidc betwee n iw fi, and second open cavities. 2 \nimLe Docket No, \ (R (L)II 104731 S₂
(O rig inal) The me thod of claim, wherein forming the bottom gate electrode comprises fortmi ng a doped r egion in a semiconductor substrate, wherein the dope d i og ion serves a s the bott om gate electrode, 3, (Origi nal) The method o f claim 1, where in the elo n gated na no- struc tu re is a nano-li i e strcture.
(O riginal) The method of claim 1, wherein the L n Lid ted nano-st ruc ture is a nano- ill oh e structure.
(Or1i ia1) The nehod of claim 1, w herein t he elongated nano-st ruc ture is for med of s1 icon.
(Ori inal) The met ho d o f c lai m 1 wherein the elon g ated nano-stru c ture is for med of a metallic material. 7 (Origin al) T he method of claim 1, wh erei n the elongated nano-strctu re i s form ci of a carb on nanotube structure. 8 (O rigin al) The mcihod of claim 1, wherein foinuijg a grphene layer comprises tuan di rang a graphen e f ilm from a su bstrate upon k hich the ? saphcne film is grown.
9. (C utiemdn0 Amended) A method of.mit111 a semiconductor device>,,E nipri i an' tonngul a bottom ate elect rode; Ca ming a first iin1ulat la yer over the bottom g ate e l ectr od e, ithe f irs t is l.ai nn layer com prising a first open cavity etched in a surface of the first i nsu lat ing lay er. wherein the first open c avi ty is;ali ned u i the botto m g ate e lec trode; f'iia ag a cn rllahe layer over an d in contact with said surf a ce of the first insu l ating l ayer; 1it Docket No \ (tlu2i 1043 2 fniing one or more sense electrodes on the uia phcne layer; Cun ingQ a seco nd ins ulai Eno layer o ver.iid in Coit ict u\ ith the ra phenblii Li the second insulati ng layer %orn pi ii a second open ca vity etched in the en 'iI ''lui I: ek ni herin 11:. 1t1E₁ t. i 'it [oh i nd ii ii " 11 the di, f.j g ca iy.......... '........}.!.... !."..i......i..l........d...h.h E r p n av t fan n m a top gate electrode over the sec ond insulat ing laver, wherein the top g ate elecio de is oli;e d with the first and second ope n cavit ies; nid Tounting an eltOntcd ni aini- tructure to a portion of 111 aphr' layer th at is; \uspeinded between the first and second open cavities.
(Oriinal) The method of claim 9. wh erein t he elongated nan o- structure is a nano- kni f e s tru cture,
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor nano-device with suspended graphene membrane
Materials described outside the worked examples.
graphene
insulating material
Patent
Atlas literature
Patent
US 8,569,089Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a 3-D perspective view of a semiconductor nano-device, according to an aspect of the invention. In general, a semiconductor nano-device 100 comprises …
FIGS. 2A, 2 B, 2C, 2 D, 2E, 2F, 2G, 2H, 2 1, 2J, 2K, 2L, 2M, 2N, 20 and 2P schematically illustrate a method for constructing a semiconductor nano-device at …
FIG. 20 after mounting an elongated nano- structure 170 on a surface of the graphene membrane 130 between the upper and lower open cavities 155 and 125. As …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
\nonie' Docket No \ (t1(2 7;i 104 2m T he li sti ng of t he Caim:. (O riginal) A method of i;n ting a. sen andfctor dce iL comprising: f1 n n i a bottom uate electrode in a substra te: in nun1112 a 114 insulat ing lax i over the \:t iaIe covering the bo ttom ode electrode; c illn a f i cavity m the first ins ulati ng la yer, wherein the first cavity is aligned with the bottom gate electrode; ti1 b, the first cavity with a second la y er of in %.n: in m ateria l: pl anar izin g t he second 1:n e t of insulatin g material using the first insulting layer as a n etch stop to fhnun a u t phln:rued ales fl, f miniig a um aphene lay er o n t h e first pl anai ied surface; linn in one or more sense electrodes on th e uraphenc L e, wherein the one or m11orle sense electrodes are disposed o n the g rap h ene l a e t adjaceni to the ini cavity; VoinL a third insulating la er over (lie 2iaphene la s ct and covering dle one or more sense electrodes; etchin g a second cavity in the thi d insuMinc la,,er. w herein the second cavity is ali g ned with the first cavity; filli n g the second cavity with a froua lh layer o f insulamino material; plaim zing the wounh layer o f insulatin g material -t'lpinC o n t he thirl insiln' lay er to fo-r a se cond pluiiiz ed surfacc: 1(m113 i a fit l insulating la y er o ver t h e second pla n arized surface, Corii iin' a top gate elccv'de over the f ifth in sulat i ng laxci. the top gate e lect rode aliied x ith the first and second cavities; dit in ' the substrate to form an individual se m ico n ducto r n u- im ucture; removing the second and fourth layers o f ins ula iin material from the first and second cav i ties, es-pcclix ely, to fo rm fi rst and second op eni. cavit i es, and mieinnlri an elongated nano-structure to a portion of the p aI phene layer that is snpciidc betwee n iw fi, and second open cavities. 2 \nimLe Docket No, \ (R (L)II 104731 S₂
(O rig inal) The me thod of claim, wherein forming the bottom gate electrode comprises fortmi ng a doped r egion in a semiconductor substrate, wherein the dope d i og ion serves a s the bott om gate electrode, 3, (Origi nal) The method o f claim 1, where in the elo n gated na no- struc tu re is a nano-li i e strcture.
(O riginal) The method of claim 1, wherein the L n Lid ted nano-st ruc ture is a nano- ill oh e structure.
(Or1i ia1) The nehod of claim 1, w herein t he elongated nano-st ruc ture is for med of s1 icon.
(Ori inal) The met ho d o f c lai m 1 wherein the elon g ated nano-stru c ture is for med of a metallic material. 7 (Origin al) T he method of claim 1, wh erei n the elongated nano-strctu re i s form ci of a carb on nanotube structure. 8 (O rigin al) The mcihod of claim 1, wherein foinuijg a grphene layer comprises tuan di rang a graphen e f ilm from a su bstrate upon k hich the ? saphcne film is grown.
9. (C utiemdn0 Amended) A method of.mit111 a semiconductor device>,,E nipri i an' tonngul a bottom ate elect rode; Ca ming a first iin1ulat la yer over the bottom g ate e l ectr od e, ithe f irs t is l.ai nn layer com prising a first open cavity etched in a surface of the first i nsu lat ing lay er. wherein the first open c avi ty is;ali ned u i the botto m g ate e lec trode; f'iia ag a cn rllahe layer over an d in contact with said surf a ce of the first insu l ating l ayer; 1it Docket No \ (tlu2i 1043 2 fniing one or more sense electrodes on the uia phcne layer; Cun ingQ a seco nd ins ulai Eno layer o ver.iid in Coit ict u\ ith the ra phenblii Li the second insulati ng layer %orn pi ii a second open ca vity etched in the en 'iI ''lui I: ek ni herin 11:. 1t1E₁ t. i 'it [oh i nd ii ii " 11 the di, f.j g ca iy.......... '........}.!.... !."..i......i..l........d...h.h E r p n av t fan n m a top gate electrode over the sec ond insulat ing laver, wherein the top g ate elecio de is oli;e d with the first and second ope n cavit ies; nid Tounting an eltOntcd ni aini- tructure to a portion of 111 aphr' layer th at is; \uspeinded between the first and second open cavities.
(Oriinal) The method of claim 9. wh erein t he elongated nan o- structure is a nano- kni f e s tru cture,
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor nano-device with suspended graphene membrane
Materials described outside the worked examples.
graphene
insulating material
Patent
Atlas literature
Patent
US 8,569,089Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a 3-D perspective view of a semiconductor nano-device, according to an aspect of the invention. In general, a semiconductor nano-device 100 comprises …
FIGS. 2A, 2 B, 2C, 2 D, 2E, 2F, 2G, 2H, 2 1, 2J, 2K, 2L, 2M, 2N, 20 and 2P schematically illustrate a method for constructing a semiconductor nano-device at …
FIG. 20 after mounting an elongated nano- structure 170 on a surface of the graphene membrane 130 between the upper and lower open cavities 155 and 125. As …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
\nonie' Docket No \ (t1(2 7;i 104 2m T he li sti ng of t he Caim:. (O riginal) A method of i;n ting a. sen andfctor dce iL comprising: f1 n n i a bottom uate electrode in a substra te: in nun1112 a 114 insulat ing lax i over the \:t iaIe covering the bo ttom ode electrode; c illn a f i cavity m the first ins ulati ng la yer, wherein the first cavity is aligned with the bottom gate electrode; ti1 b, the first cavity with a second la y er of in %.n: in m ateria l: pl anar izin g t he second 1:n e t of insulatin g material using the first insulting layer as a n etch stop to fhnun a u t phln:rued ales fl, f miniig a um aphene lay er o n t h e first pl anai ied surface; linn in one or more sense electrodes on th e uraphenc L e, wherein the one or m11orle sense electrodes are disposed o n the g rap h ene l a e t adjaceni to the ini cavity; VoinL a third insulating la er over (lie 2iaphene la s ct and covering dle one or more sense electrodes; etchin g a second cavity in the thi d insuMinc la,,er. w herein the second cavity is ali g ned with the first cavity; filli n g the second cavity with a froua lh layer o f insulamino material; plaim zing the wounh layer o f insulatin g material -t'lpinC o n t he thirl insiln' lay er to fo-r a se cond pluiiiz ed surfacc: 1(m113 i a fit l insulating la y er o ver t h e second pla n arized surface, Corii iin' a top gate elccv'de over the f ifth in sulat i ng laxci. the top gate e lect rode aliied x ith the first and second cavities; dit in ' the substrate to form an individual se m ico n ducto r n u- im ucture; removing the second and fourth layers o f ins ula iin material from the first and second cav i ties, es-pcclix ely, to fo rm fi rst and second op eni. cavit i es, and mieinnlri an elongated nano-structure to a portion of the p aI phene layer that is snpciidc betwee n iw fi, and second open cavities. 2 \nimLe Docket No, \ (R (L)II 104731 S₂
(O rig inal) The me thod of claim, wherein forming the bottom gate electrode comprises fortmi ng a doped r egion in a semiconductor substrate, wherein the dope d i og ion serves a s the bott om gate electrode, 3, (Origi nal) The method o f claim 1, where in the elo n gated na no- struc tu re is a nano-li i e strcture.
(O riginal) The method of claim 1, wherein the L n Lid ted nano-st ruc ture is a nano- ill oh e structure.
(Or1i ia1) The nehod of claim 1, w herein t he elongated nano-st ruc ture is for med of s1 icon.
(Ori inal) The met ho d o f c lai m 1 wherein the elon g ated nano-stru c ture is for med of a metallic material. 7 (Origin al) T he method of claim 1, wh erei n the elongated nano-strctu re i s form ci of a carb on nanotube structure. 8 (O rigin al) The mcihod of claim 1, wherein foinuijg a grphene layer comprises tuan di rang a graphen e f ilm from a su bstrate upon k hich the ? saphcne film is grown.
9. (C utiemdn0 Amended) A method of.mit111 a semiconductor device>,,E nipri i an' tonngul a bottom ate elect rode; Ca ming a first iin1ulat la yer over the bottom g ate e l ectr od e, ithe f irs t is l.ai nn layer com prising a first open cavity etched in a surface of the first i nsu lat ing lay er. wherein the first open c avi ty is;ali ned u i the botto m g ate e lec trode; f'iia ag a cn rllahe layer over an d in contact with said surf a ce of the first insu l ating l ayer; 1it Docket No \ (tlu2i 1043 2 fniing one or more sense electrodes on the uia phcne layer; Cun ingQ a seco nd ins ulai Eno layer o ver.iid in Coit ict u\ ith the ra phenblii Li the second insulati ng layer %orn pi ii a second open ca vity etched in the en 'iI ''lui I: ek ni herin 11:. 1t1E₁ t. i 'it [oh i nd ii ii " 11 the di, f.j g ca iy.......... '........}.!.... !."..i......i..l........d...h.h E r p n av t fan n m a top gate electrode over the sec ond insulat ing laver, wherein the top g ate elecio de is oli;e d with the first and second ope n cavit ies; nid Tounting an eltOntcd ni aini- tructure to a portion of 111 aphr' layer th at is; \uspeinded between the first and second open cavities.
(Oriinal) The method of claim 9. wh erein t he elongated nan o- structure is a nano- kni f e s tru cture,
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor nano-device with suspended graphene membrane
Materials described outside the worked examples.
graphene
insulating material
silicon
Si
metallic material
carbon nanotube
silicon
Si
metallic material
carbon nanotube
silicon
Si
metallic material
carbon nanotube
silicon
Si
metallic material
carbon nanotube
