Patent
US 8,980,759Patent
Atlas literature
Patent
US 8,980,759Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a method of fabricating a slanted field plate gate in accordance with the present disclosure; [0023]
FIG. 2 shows an alternative method of fabricating a slanted field plate gate in accordance with the present disclosure; [0024]
FIG. 3A shows a sloped hydrogen silsesquioxane (HSQ) coating after SiN is deposited on the initial HSQ layer, and FIG s. 3B and 3 C show the linear slope …
FIG. 4A shows a SEM image of a HSQ slope,
FIG. 5 shows the uniformity achieved for the sloped gate feature across a 3 inch single-side polished silicon wafer in accordance with the present disclosure; …
FIG. 6 shows TEM cross-section of a completed sloped field plate gate on GaN in accordance with the present disclosure; [0028]
FIG. 7B shows a subsequent slope formed in an underlying PECVD SiN after 8 reactive ion etching (RIE) etching, with corresponding calculated voltages to …
FIG. 8 shows a cross-sectional TEM image of a FET gate with a slant field plate formed by coating HSQ over a step and replication into underlying PECVD SiN in …
FIG. 9A. In this process, multiple coats of HSQ are coated on the SiN 40 and HSQ steps 70, 72 and 74 are formed using electron-beam lithography, as shown in …
FIG. 10 shows an alternative method of fabrication of a slanted gate field plate of arbitrary slope and curvature using multiple HSQ steps in accordance with …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; forming a wall on the epitaxy near a drain of the FET, the wall comprising a first negative tone electron-beam resist; depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET; depositing a second negative tone electron-beam resist over the dielectric, wherein surface tension causes the deposited second negative tone electron-beam resist to have a slanted top surface between the step and a source of the FET; etching anisotropically vertically the second negative tone electron-beam resist and the dielectric to remove the second negative tone electron-beam resist and to transfer a shape of the slanted top surface to the dielectric between the step and the source of the FET; and forming a gatehead comprising metal on the dielectric between the step and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 1 wherein: the first negative tone electron-beam resist comprises hydrogen silsesquioxane (HSQ) having a 50% to 100% HSQ concentration; and the second negative tone electron-beam resist comprises HSQ having a.01% to 20% HSQ concentration.
The method of claim 1 wherein: 21 a slant angle of the slanted field plate depends on a height of the step, and an etch rate of the second negative tone electron-beam resist versus an etch rate of the dielectric.
The method of claim 1 further comprising removing the first negative tone electron-beam resist using a wet etch.
The method of claim 1 wherein the dielectric comprises SiN, Si O2, SiON, SiCN, A 1 203 or Hf
The method of claim 1 further comprising: etching a gatefoot in the dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; depositing first dielectric on the epitaxy by plasma- enhanced chemical vapor deposition (PECVD), the first dielectric having a thickness corresponding to a desired maximum slant height; depositing a second dielectric on the first dielectric to form a wall near a drain of the FET; depositing a negative tone electron-beam resist on the first and the second dielectric, wherein surface tension causes the deposited negative tone electron-beam resist to have a slanted top surface between the wall and a source of the FET; etching anisotropically vertically the negative tone electron-beam resist, the first dielectric and the second 22 dielectric to remove the negative tone electron-beam resist and to transfer a shape of the slanted top surface to the first dielectric between the wall and the source of the FET; and forming a gatehead comprising metal on the dielectric between the wall and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 7 wherein the negative tone electron- beam resist comprises hydrogen silsesquioxane (HSQ) having a.01 % to 20% HSQ concentration.
The method of claim 7 wherein the first and the second dielectric comprises SiN, SiO2, SiON, Si C N, A 120 3 or Hf O 2, and the second dielectric is deposited using plasma-enhanced chemical vapor deposition (PECVD).
The method of claim 7 further comprising: etching a gatefoot in the first dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
The method of claim 7 wherein: a slant angle of the slanted field plate depends on a height of the step, and an etch rate of the negative tone electron-beam resist versus an etch rate of the first dielectric.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; 23 depositing a first dielectric on the epitaxy; forming first negative tone electron-beam resist on the first dielectric near a source of the FET; depositing second dielectric over the first dielectric and the first negative tone electron-beam resist; planarizing the second dielectric and the first negative tone electron-beam resist using chemical-mechanical polishing (CMP); forming second negative tone electron-beam resist on the over the first negative tone electron-beam resist and the second dielectric near a source of the FET, the second negative tone electron-beam resist having a longer lateral length than the first negative tone electron-beam resist; depositing third dielectric over the second dielectric and the second negative tone electron-beam resist; planarizing the third dielectric and the second negative tone electron-beam resist using chemical-mechanical polishing (CMP); removing the first negative tone electron-beam resist and the second negative tone electron-beam resist by wet etching, wherein the second dielectric forms a first step from the first dielectric, and the third dielectric forms a second step from the second dielectric; depositing third negative tone electron-beam resist over the first, second and third dielectric, wherein surface tension causes the deposited third negative tone electron- beam resist to have a slanted top surface between the first step and a source of the FET, and between the second step and the first step; etching anisotropically vertically the third negative tone electron-beam resist and the first, second and third dielectric to remove the third negative tone electron-beam 24 resist and to transfer a shape of the slanted top surface to the first, second and third dielectric between the second step and the source of the FET; and forming a gatehead comprising metal on the first, second and third dielectric between the second step and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 12 wherein: the third negative tone electron-beam resist comprises hydrogen silsesquioxane (HSQ) having a.01 % to 20% HSQ concentration.
The method of claim 12 wherein the first, second and third dielectric comprises SiN, SiO2, SiON, SiCN, A 120 3 or HfO2, and the dielectric is deposited using plasma-enhanced chemical vapor deposition (PECVD).
The method of claim 12 further comprising: etching a gatefoot in the first dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
The method of claim 12 wherein etching anisotropically vertically comprises tetrafluoromethane (C F₄) based reactive ion etching.
The method of claim 12 further comprising smoothing the shape of the slanted top surface by using an isotropic chemical etch.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; depositing a dielectric on the epitaxy; forming a first negative tone electron-beam resist on the dielectric near a drain of the FET to form a first step; depositing second negative tone electron-beam resist dielectric over the first negative tone electron-beam resist and near a drain of the FET to form a second step, the second negative tone electron-beam resist having a lateral length less than the first negative tone electron-beam resist; depositing third negative tone electron-beam resist over the first and second negative tone electron-beam resist, wherein surface tension causes the deposited third negative tone electron-beam resist to have a slanted top surface between the first step and a source of the FET, and between the second step and the first step; etching anisotropically vertically the first, second and third negative tone electron-beam resist to remove the first, second and third negative tone electron-beam resist and to transfer a shape of the slanted top surface to the dielectric between the second step and the source of the FET; and forming a gatehead comprising metal on the dielectric between the second step and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 18 wherein: the first, second and third negative tone electron-beam resist comprise HSQ having a.01 % to 20% HSQ concentration.
The method of claim 18 wherein the dielectric comprises SiN, Si O2, SiON, Si C N, A 120 3 or Hf 02.
The method of claim 18 further comprising: etching a gatefoot in the dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
The method of claim 18 wherein etching anisotropically vertically comprises tetrafluoromethane (C F₄) based reactive ion etching.
The method of claim 18 further comprising smoothing the shape of the slanted top surface by using an isotropic chemical etch. 27
Layer stacks claimed or described, ordered top of device to substrate.
slanted field plate GaN HEMT/field effect transistor
Materials described outside the worked examples.
epitaxy for FET
negative tone electron-beam resist
dielectric
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4A shows a SEM image of a HSQ slope,
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,980,759Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a method of fabricating a slanted field plate gate in accordance with the present disclosure; [0023]
FIG. 2 shows an alternative method of fabricating a slanted field plate gate in accordance with the present disclosure; [0024]
FIG. 3A shows a sloped hydrogen silsesquioxane (HSQ) coating after SiN is deposited on the initial HSQ layer, and FIG s. 3B and 3 C show the linear slope …
FIG. 4A shows a SEM image of a HSQ slope,
FIG. 5 shows the uniformity achieved for the sloped gate feature across a 3 inch single-side polished silicon wafer in accordance with the present disclosure; …
FIG. 6 shows TEM cross-section of a completed sloped field plate gate on GaN in accordance with the present disclosure; [0028]
FIG. 7B shows a subsequent slope formed in an underlying PECVD SiN after 8 reactive ion etching (RIE) etching, with corresponding calculated voltages to …
FIG. 8 shows a cross-sectional TEM image of a FET gate with a slant field plate formed by coating HSQ over a step and replication into underlying PECVD SiN in …
FIG. 9A. In this process, multiple coats of HSQ are coated on the SiN 40 and HSQ steps 70, 72 and 74 are formed using electron-beam lithography, as shown in …
FIG. 10 shows an alternative method of fabrication of a slanted gate field plate of arbitrary slope and curvature using multiple HSQ steps in accordance with …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; forming a wall on the epitaxy near a drain of the FET, the wall comprising a first negative tone electron-beam resist; depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET; depositing a second negative tone electron-beam resist over the dielectric, wherein surface tension causes the deposited second negative tone electron-beam resist to have a slanted top surface between the step and a source of the FET; etching anisotropically vertically the second negative tone electron-beam resist and the dielectric to remove the second negative tone electron-beam resist and to transfer a shape of the slanted top surface to the dielectric between the step and the source of the FET; and forming a gatehead comprising metal on the dielectric between the step and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 1 wherein: the first negative tone electron-beam resist comprises hydrogen silsesquioxane (HSQ) having a 50% to 100% HSQ concentration; and the second negative tone electron-beam resist comprises HSQ having a.01% to 20% HSQ concentration.
The method of claim 1 wherein: 21 a slant angle of the slanted field plate depends on a height of the step, and an etch rate of the second negative tone electron-beam resist versus an etch rate of the dielectric.
The method of claim 1 further comprising removing the first negative tone electron-beam resist using a wet etch.
The method of claim 1 wherein the dielectric comprises SiN, Si O2, SiON, SiCN, A 1 203 or Hf
The method of claim 1 further comprising: etching a gatefoot in the dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; depositing first dielectric on the epitaxy by plasma- enhanced chemical vapor deposition (PECVD), the first dielectric having a thickness corresponding to a desired maximum slant height; depositing a second dielectric on the first dielectric to form a wall near a drain of the FET; depositing a negative tone electron-beam resist on the first and the second dielectric, wherein surface tension causes the deposited negative tone electron-beam resist to have a slanted top surface between the wall and a source of the FET; etching anisotropically vertically the negative tone electron-beam resist, the first dielectric and the second 22 dielectric to remove the negative tone electron-beam resist and to transfer a shape of the slanted top surface to the first dielectric between the wall and the source of the FET; and forming a gatehead comprising metal on the dielectric between the wall and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 7 wherein the negative tone electron- beam resist comprises hydrogen silsesquioxane (HSQ) having a.01 % to 20% HSQ concentration.
The method of claim 7 wherein the first and the second dielectric comprises SiN, SiO2, SiON, Si C N, A 120 3 or Hf O 2, and the second dielectric is deposited using plasma-enhanced chemical vapor deposition (PECVD).
The method of claim 7 further comprising: etching a gatefoot in the first dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
The method of claim 7 wherein: a slant angle of the slanted field plate depends on a height of the step, and an etch rate of the negative tone electron-beam resist versus an etch rate of the first dielectric.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; 23 depositing a first dielectric on the epitaxy; forming first negative tone electron-beam resist on the first dielectric near a source of the FET; depositing second dielectric over the first dielectric and the first negative tone electron-beam resist; planarizing the second dielectric and the first negative tone electron-beam resist using chemical-mechanical polishing (CMP); forming second negative tone electron-beam resist on the over the first negative tone electron-beam resist and the second dielectric near a source of the FET, the second negative tone electron-beam resist having a longer lateral length than the first negative tone electron-beam resist; depositing third dielectric over the second dielectric and the second negative tone electron-beam resist; planarizing the third dielectric and the second negative tone electron-beam resist using chemical-mechanical polishing (CMP); removing the first negative tone electron-beam resist and the second negative tone electron-beam resist by wet etching, wherein the second dielectric forms a first step from the first dielectric, and the third dielectric forms a second step from the second dielectric; depositing third negative tone electron-beam resist over the first, second and third dielectric, wherein surface tension causes the deposited third negative tone electron- beam resist to have a slanted top surface between the first step and a source of the FET, and between the second step and the first step; etching anisotropically vertically the third negative tone electron-beam resist and the first, second and third dielectric to remove the third negative tone electron-beam 24 resist and to transfer a shape of the slanted top surface to the first, second and third dielectric between the second step and the source of the FET; and forming a gatehead comprising metal on the first, second and third dielectric between the second step and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 12 wherein: the third negative tone electron-beam resist comprises hydrogen silsesquioxane (HSQ) having a.01 % to 20% HSQ concentration.
The method of claim 12 wherein the first, second and third dielectric comprises SiN, SiO2, SiON, SiCN, A 120 3 or HfO2, and the dielectric is deposited using plasma-enhanced chemical vapor deposition (PECVD).
The method of claim 12 further comprising: etching a gatefoot in the first dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
The method of claim 12 wherein etching anisotropically vertically comprises tetrafluoromethane (C F₄) based reactive ion etching.
The method of claim 12 further comprising smoothing the shape of the slanted top surface by using an isotropic chemical etch.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; depositing a dielectric on the epitaxy; forming a first negative tone electron-beam resist on the dielectric near a drain of the FET to form a first step; depositing second negative tone electron-beam resist dielectric over the first negative tone electron-beam resist and near a drain of the FET to form a second step, the second negative tone electron-beam resist having a lateral length less than the first negative tone electron-beam resist; depositing third negative tone electron-beam resist over the first and second negative tone electron-beam resist, wherein surface tension causes the deposited third negative tone electron-beam resist to have a slanted top surface between the first step and a source of the FET, and between the second step and the first step; etching anisotropically vertically the first, second and third negative tone electron-beam resist to remove the first, second and third negative tone electron-beam resist and to transfer a shape of the slanted top surface to the dielectric between the second step and the source of the FET; and forming a gatehead comprising metal on the dielectric between the second step and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 18 wherein: the first, second and third negative tone electron-beam resist comprise HSQ having a.01 % to 20% HSQ concentration.
The method of claim 18 wherein the dielectric comprises SiN, Si O2, SiON, Si C N, A 120 3 or Hf 02.
The method of claim 18 further comprising: etching a gatefoot in the dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
The method of claim 18 wherein etching anisotropically vertically comprises tetrafluoromethane (C F₄) based reactive ion etching.
The method of claim 18 further comprising smoothing the shape of the slanted top surface by using an isotropic chemical etch. 27
Layer stacks claimed or described, ordered top of device to substrate.
slanted field plate GaN HEMT/field effect transistor
Materials described outside the worked examples.
epitaxy for FET
negative tone electron-beam resist
dielectric
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4A shows a SEM image of a HSQ slope,
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 8,980,759Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a method of fabricating a slanted field plate gate in accordance with the present disclosure; [0023]
FIG. 2 shows an alternative method of fabricating a slanted field plate gate in accordance with the present disclosure; [0024]
FIG. 3A shows a sloped hydrogen silsesquioxane (HSQ) coating after SiN is deposited on the initial HSQ layer, and FIG s. 3B and 3 C show the linear slope …
FIG. 4A shows a SEM image of a HSQ slope,
FIG. 5 shows the uniformity achieved for the sloped gate feature across a 3 inch single-side polished silicon wafer in accordance with the present disclosure; …
FIG. 6 shows TEM cross-section of a completed sloped field plate gate on GaN in accordance with the present disclosure; [0028]
FIG. 7B shows a subsequent slope formed in an underlying PECVD SiN after 8 reactive ion etching (RIE) etching, with corresponding calculated voltages to …
FIG. 8 shows a cross-sectional TEM image of a FET gate with a slant field plate formed by coating HSQ over a step and replication into underlying PECVD SiN in …
FIG. 9A. In this process, multiple coats of HSQ are coated on the SiN 40 and HSQ steps 70, 72 and 74 are formed using electron-beam lithography, as shown in …
FIG. 10 shows an alternative method of fabrication of a slanted gate field plate of arbitrary slope and curvature using multiple HSQ steps in accordance with …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; forming a wall on the epitaxy near a drain of the FET, the wall comprising a first negative tone electron-beam resist; depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET; depositing a second negative tone electron-beam resist over the dielectric, wherein surface tension causes the deposited second negative tone electron-beam resist to have a slanted top surface between the step and a source of the FET; etching anisotropically vertically the second negative tone electron-beam resist and the dielectric to remove the second negative tone electron-beam resist and to transfer a shape of the slanted top surface to the dielectric between the step and the source of the FET; and forming a gatehead comprising metal on the dielectric between the step and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 1 wherein: the first negative tone electron-beam resist comprises hydrogen silsesquioxane (HSQ) having a 50% to 100% HSQ concentration; and the second negative tone electron-beam resist comprises HSQ having a.01% to 20% HSQ concentration.
The method of claim 1 wherein: 21 a slant angle of the slanted field plate depends on a height of the step, and an etch rate of the second negative tone electron-beam resist versus an etch rate of the dielectric.
The method of claim 1 further comprising removing the first negative tone electron-beam resist using a wet etch.
The method of claim 1 wherein the dielectric comprises SiN, Si O2, SiON, SiCN, A 1 203 or Hf
The method of claim 1 further comprising: etching a gatefoot in the dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; depositing first dielectric on the epitaxy by plasma- enhanced chemical vapor deposition (PECVD), the first dielectric having a thickness corresponding to a desired maximum slant height; depositing a second dielectric on the first dielectric to form a wall near a drain of the FET; depositing a negative tone electron-beam resist on the first and the second dielectric, wherein surface tension causes the deposited negative tone electron-beam resist to have a slanted top surface between the wall and a source of the FET; etching anisotropically vertically the negative tone electron-beam resist, the first dielectric and the second 22 dielectric to remove the negative tone electron-beam resist and to transfer a shape of the slanted top surface to the first dielectric between the wall and the source of the FET; and forming a gatehead comprising metal on the dielectric between the wall and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 7 wherein the negative tone electron- beam resist comprises hydrogen silsesquioxane (HSQ) having a.01 % to 20% HSQ concentration.
The method of claim 7 wherein the first and the second dielectric comprises SiN, SiO2, SiON, Si C N, A 120 3 or Hf O 2, and the second dielectric is deposited using plasma-enhanced chemical vapor deposition (PECVD).
The method of claim 7 further comprising: etching a gatefoot in the first dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
The method of claim 7 wherein: a slant angle of the slanted field plate depends on a height of the step, and an etch rate of the negative tone electron-beam resist versus an etch rate of the first dielectric.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; 23 depositing a first dielectric on the epitaxy; forming first negative tone electron-beam resist on the first dielectric near a source of the FET; depositing second dielectric over the first dielectric and the first negative tone electron-beam resist; planarizing the second dielectric and the first negative tone electron-beam resist using chemical-mechanical polishing (CMP); forming second negative tone electron-beam resist on the over the first negative tone electron-beam resist and the second dielectric near a source of the FET, the second negative tone electron-beam resist having a longer lateral length than the first negative tone electron-beam resist; depositing third dielectric over the second dielectric and the second negative tone electron-beam resist; planarizing the third dielectric and the second negative tone electron-beam resist using chemical-mechanical polishing (CMP); removing the first negative tone electron-beam resist and the second negative tone electron-beam resist by wet etching, wherein the second dielectric forms a first step from the first dielectric, and the third dielectric forms a second step from the second dielectric; depositing third negative tone electron-beam resist over the first, second and third dielectric, wherein surface tension causes the deposited third negative tone electron- beam resist to have a slanted top surface between the first step and a source of the FET, and between the second step and the first step; etching anisotropically vertically the third negative tone electron-beam resist and the first, second and third dielectric to remove the third negative tone electron-beam 24 resist and to transfer a shape of the slanted top surface to the first, second and third dielectric between the second step and the source of the FET; and forming a gatehead comprising metal on the first, second and third dielectric between the second step and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 12 wherein: the third negative tone electron-beam resist comprises hydrogen silsesquioxane (HSQ) having a.01 % to 20% HSQ concentration.
The method of claim 12 wherein the first, second and third dielectric comprises SiN, SiO2, SiON, SiCN, A 120 3 or HfO2, and the dielectric is deposited using plasma-enhanced chemical vapor deposition (PECVD).
The method of claim 12 further comprising: etching a gatefoot in the first dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
The method of claim 12 wherein etching anisotropically vertically comprises tetrafluoromethane (C F₄) based reactive ion etching.
The method of claim 12 further comprising smoothing the shape of the slanted top surface by using an isotropic chemical etch.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; depositing a dielectric on the epitaxy; forming a first negative tone electron-beam resist on the dielectric near a drain of the FET to form a first step; depositing second negative tone electron-beam resist dielectric over the first negative tone electron-beam resist and near a drain of the FET to form a second step, the second negative tone electron-beam resist having a lateral length less than the first negative tone electron-beam resist; depositing third negative tone electron-beam resist over the first and second negative tone electron-beam resist, wherein surface tension causes the deposited third negative tone electron-beam resist to have a slanted top surface between the first step and a source of the FET, and between the second step and the first step; etching anisotropically vertically the first, second and third negative tone electron-beam resist to remove the first, second and third negative tone electron-beam resist and to transfer a shape of the slanted top surface to the dielectric between the second step and the source of the FET; and forming a gatehead comprising metal on the dielectric between the second step and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 18 wherein: the first, second and third negative tone electron-beam resist comprise HSQ having a.01 % to 20% HSQ concentration.
The method of claim 18 wherein the dielectric comprises SiN, Si O2, SiON, Si C N, A 120 3 or Hf 02.
The method of claim 18 further comprising: etching a gatefoot in the dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
The method of claim 18 wherein etching anisotropically vertically comprises tetrafluoromethane (C F₄) based reactive ion etching.
The method of claim 18 further comprising smoothing the shape of the slanted top surface by using an isotropic chemical etch. 27
Layer stacks claimed or described, ordered top of device to substrate.
slanted field plate GaN HEMT/field effect transistor
Materials described outside the worked examples.
epitaxy for FET
negative tone electron-beam resist
dielectric
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4A shows a SEM image of a HSQ slope,
Related documents with shared materials, methods, properties, or citations.
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Atlas literature
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US 8,980,759Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a method of fabricating a slanted field plate gate in accordance with the present disclosure; [0023]
FIG. 2 shows an alternative method of fabricating a slanted field plate gate in accordance with the present disclosure; [0024]
FIG. 3A shows a sloped hydrogen silsesquioxane (HSQ) coating after SiN is deposited on the initial HSQ layer, and FIG s. 3B and 3 C show the linear slope …
FIG. 4A shows a SEM image of a HSQ slope,
FIG. 5 shows the uniformity achieved for the sloped gate feature across a 3 inch single-side polished silicon wafer in accordance with the present disclosure; …
FIG. 6 shows TEM cross-section of a completed sloped field plate gate on GaN in accordance with the present disclosure; [0028]
FIG. 7B shows a subsequent slope formed in an underlying PECVD SiN after 8 reactive ion etching (RIE) etching, with corresponding calculated voltages to …
FIG. 8 shows a cross-sectional TEM image of a FET gate with a slant field plate formed by coating HSQ over a step and replication into underlying PECVD SiN in …
FIG. 9A. In this process, multiple coats of HSQ are coated on the SiN 40 and HSQ steps 70, 72 and 74 are formed using electron-beam lithography, as shown in …
FIG. 10 shows an alternative method of fabrication of a slanted gate field plate of arbitrary slope and curvature using multiple HSQ steps in accordance with …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; forming a wall on the epitaxy near a drain of the FET, the wall comprising a first negative tone electron-beam resist; depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET; depositing a second negative tone electron-beam resist over the dielectric, wherein surface tension causes the deposited second negative tone electron-beam resist to have a slanted top surface between the step and a source of the FET; etching anisotropically vertically the second negative tone electron-beam resist and the dielectric to remove the second negative tone electron-beam resist and to transfer a shape of the slanted top surface to the dielectric between the step and the source of the FET; and forming a gatehead comprising metal on the dielectric between the step and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 1 wherein: the first negative tone electron-beam resist comprises hydrogen silsesquioxane (HSQ) having a 50% to 100% HSQ concentration; and the second negative tone electron-beam resist comprises HSQ having a.01% to 20% HSQ concentration.
The method of claim 1 wherein: 21 a slant angle of the slanted field plate depends on a height of the step, and an etch rate of the second negative tone electron-beam resist versus an etch rate of the dielectric.
The method of claim 1 further comprising removing the first negative tone electron-beam resist using a wet etch.
The method of claim 1 wherein the dielectric comprises SiN, Si O2, SiON, SiCN, A 1 203 or Hf
The method of claim 1 further comprising: etching a gatefoot in the dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; depositing first dielectric on the epitaxy by plasma- enhanced chemical vapor deposition (PECVD), the first dielectric having a thickness corresponding to a desired maximum slant height; depositing a second dielectric on the first dielectric to form a wall near a drain of the FET; depositing a negative tone electron-beam resist on the first and the second dielectric, wherein surface tension causes the deposited negative tone electron-beam resist to have a slanted top surface between the wall and a source of the FET; etching anisotropically vertically the negative tone electron-beam resist, the first dielectric and the second 22 dielectric to remove the negative tone electron-beam resist and to transfer a shape of the slanted top surface to the first dielectric between the wall and the source of the FET; and forming a gatehead comprising metal on the dielectric between the wall and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 7 wherein the negative tone electron- beam resist comprises hydrogen silsesquioxane (HSQ) having a.01 % to 20% HSQ concentration.
The method of claim 7 wherein the first and the second dielectric comprises SiN, SiO2, SiON, Si C N, A 120 3 or Hf O 2, and the second dielectric is deposited using plasma-enhanced chemical vapor deposition (PECVD).
The method of claim 7 further comprising: etching a gatefoot in the first dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
The method of claim 7 wherein: a slant angle of the slanted field plate depends on a height of the step, and an etch rate of the negative tone electron-beam resist versus an etch rate of the first dielectric.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; 23 depositing a first dielectric on the epitaxy; forming first negative tone electron-beam resist on the first dielectric near a source of the FET; depositing second dielectric over the first dielectric and the first negative tone electron-beam resist; planarizing the second dielectric and the first negative tone electron-beam resist using chemical-mechanical polishing (CMP); forming second negative tone electron-beam resist on the over the first negative tone electron-beam resist and the second dielectric near a source of the FET, the second negative tone electron-beam resist having a longer lateral length than the first negative tone electron-beam resist; depositing third dielectric over the second dielectric and the second negative tone electron-beam resist; planarizing the third dielectric and the second negative tone electron-beam resist using chemical-mechanical polishing (CMP); removing the first negative tone electron-beam resist and the second negative tone electron-beam resist by wet etching, wherein the second dielectric forms a first step from the first dielectric, and the third dielectric forms a second step from the second dielectric; depositing third negative tone electron-beam resist over the first, second and third dielectric, wherein surface tension causes the deposited third negative tone electron- beam resist to have a slanted top surface between the first step and a source of the FET, and between the second step and the first step; etching anisotropically vertically the third negative tone electron-beam resist and the first, second and third dielectric to remove the third negative tone electron-beam 24 resist and to transfer a shape of the slanted top surface to the first, second and third dielectric between the second step and the source of the FET; and forming a gatehead comprising metal on the first, second and third dielectric between the second step and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 12 wherein: the third negative tone electron-beam resist comprises hydrogen silsesquioxane (HSQ) having a.01 % to 20% HSQ concentration.
The method of claim 12 wherein the first, second and third dielectric comprises SiN, SiO2, SiON, SiCN, A 120 3 or HfO2, and the dielectric is deposited using plasma-enhanced chemical vapor deposition (PECVD).
The method of claim 12 further comprising: etching a gatefoot in the first dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
The method of claim 12 wherein etching anisotropically vertically comprises tetrafluoromethane (C F₄) based reactive ion etching.
The method of claim 12 further comprising smoothing the shape of the slanted top surface by using an isotropic chemical etch.
A method of forming a slanted field plate comprising: forming epitaxy for a field effect transistor (FET) on a substrate; depositing a dielectric on the epitaxy; forming a first negative tone electron-beam resist on the dielectric near a drain of the FET to form a first step; depositing second negative tone electron-beam resist dielectric over the first negative tone electron-beam resist and near a drain of the FET to form a second step, the second negative tone electron-beam resist having a lateral length less than the first negative tone electron-beam resist; depositing third negative tone electron-beam resist over the first and second negative tone electron-beam resist, wherein surface tension causes the deposited third negative tone electron-beam resist to have a slanted top surface between the first step and a source of the FET, and between the second step and the first step; etching anisotropically vertically the first, second and third negative tone electron-beam resist to remove the first, second and third negative tone electron-beam resist and to transfer a shape of the slanted top surface to the dielectric between the second step and the source of the FET; and forming a gatehead comprising metal on the dielectric between the second step and the source of the FET; wherein the gatehead forms a slanted field plate.
The method of claim 18 wherein: the first, second and third negative tone electron-beam resist comprise HSQ having a.01 % to 20% HSQ concentration.
The method of claim 18 wherein the dielectric comprises SiN, Si O2, SiON, Si C N, A 120 3 or Hf 02.
The method of claim 18 further comprising: etching a gatefoot in the dielectric near the source; wherein forming the gatehead further comprises forming the gatehead in the gatefoot.
The method of claim 18 wherein etching anisotropically vertically comprises tetrafluoromethane (C F₄) based reactive ion etching.
The method of claim 18 further comprising smoothing the shape of the slanted top surface by using an isotropic chemical etch. 27
Layer stacks claimed or described, ordered top of device to substrate.
slanted field plate GaN HEMT/field effect transistor
Materials described outside the worked examples.
epitaxy for FET
negative tone electron-beam resist
dielectric
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4A shows a SEM image of a HSQ slope,
Related documents with shared materials, methods, properties, or citations.
hydrogen silsesquioxane (HSQ) 50-100% concentration
HSQ
dielectric: SiN, SiO2, SiON, SiCN, Al₂O3, or HfO₂
tetrafluoromethane
CF₄
GaN
FIG. 6 shows TEM cross-section of a completed sloped field plate gate on GaN in accordance with the present disclosure; [0028]
FIG. 8 shows a cross-sectional TEM image of a FET gate with a slant field plate formed by coating HSQ over a step and replication into underlying PECVD SiN in …
FIG. 8 shows a cross-sectional TEM image of a FET gate with a slant field plate formed by coating HSQ over a step and replication into underlying PECVD SiN in …
hydrogen silsesquioxane (HSQ) 50-100% concentration
HSQ
dielectric: SiN, SiO2, SiON, SiCN, Al₂O3, or HfO₂
tetrafluoromethane
CF₄
GaN
FIG. 6 shows TEM cross-section of a completed sloped field plate gate on GaN in accordance with the present disclosure; [0028]
FIG. 8 shows a cross-sectional TEM image of a FET gate with a slant field plate formed by coating HSQ over a step and replication into underlying PECVD SiN in …
FIG. 8 shows a cross-sectional TEM image of a FET gate with a slant field plate formed by coating HSQ over a step and replication into underlying PECVD SiN in …
hydrogen silsesquioxane (HSQ) 50-100% concentration
HSQ
dielectric: SiN, SiO2, SiON, SiCN, Al₂O3, or HfO₂
tetrafluoromethane
CF₄
GaN
FIG. 6 shows TEM cross-section of a completed sloped field plate gate on GaN in accordance with the present disclosure; [0028]
FIG. 8 shows a cross-sectional TEM image of a FET gate with a slant field plate formed by coating HSQ over a step and replication into underlying PECVD SiN in …
FIG. 8 shows a cross-sectional TEM image of a FET gate with a slant field plate formed by coating HSQ over a step and replication into underlying PECVD SiN in …
hydrogen silsesquioxane (HSQ) 50-100% concentration
HSQ
dielectric: SiN, SiO2, SiON, SiCN, Al₂O3, or HfO₂
tetrafluoromethane
CF₄
GaN
FIG. 6 shows TEM cross-section of a completed sloped field plate gate on GaN in accordance with the present disclosure; [0028]
FIG. 8 shows a cross-sectional TEM image of a FET gate with a slant field plate formed by coating HSQ over a step and replication into underlying PECVD SiN in …
FIG. 8 shows a cross-sectional TEM image of a FET gate with a slant field plate formed by coating HSQ over a step and replication into underlying PECVD SiN in …
