Patent
US 9,349,825METHOD FOR MANUFACTURING GRAPHENE TRANSISTOR BASED ON SELF-ALIGNING TECHNOLOGY
Zhihong FENG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,349,825Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for producing a graphene transistor based on self-aligning technology comprising: 1) forming a graphene layer (4) on a substrate (1); 2) depositing a metal layer (5) on the graphene layer (4); 3) covering a des i red region on the metal layer (5) with a photoresist pattern (6); 4) using the photoresist pattern (6) as a mask to remove an exposed metal; 5) using the photoresist pattern (6) as a mask to etch away an exposed graphene prior to removing the photoresist; 6) forming metal electrodes of a source electrode (7), gate electrode (8) and drain electrode (9), wherein the source electrode (7) and drain electrode (9) are connected with a metal of the active region; 7) forming a gate mask patte rn (10) from a photoresist between the source electrode (7) and the drain electrode (9); 8) using the gate pattern of photoresist as a mask to remove an exposed metal; 9) forming a gate dielectric seed layer (11) on an exposed graphene layer (4) by using the gate pattern of photoresist as a mask; 10) forming a gate dielectric (12) on the gate dielectric seed layer; 11) forming a gate metal (13) on the gate dielectric and removing the photoresist.
The method of claim 1, wherein the method further comprises the following step 12): forming a self-aligning metal (14) by means of the mask function of the gate metal with self-aligning, wherein the gate cap of the gate metal has a larger width than that of the gate base.
The method of claim 1, wherein the substrate is an insulation layer 13 (2) made of SixOy, Si XNy, BN, A lXOy, Hf XOy, A lXNy, SiC, Si, Sapphire, glass, polyethylene terephthalate material, polyi mi de, polydimethyl siloxane or the combination thereof, wherein x = 0.5 to 3, Y = 0 to 2.
The method of claim 1, wherein the graphene layer (4) in the step 1) is deposited directly or epitaxially grow on the substrate (1) or another material, and it is transferred onto the substrate by peeling off, wherein the graphene layer (4) has one or more layers.
The method of claim 1, wherein the metal layer (5) in the step 2) is a metal that can be corroded by a chemical solution, which is selected from the group consisting of Au, Ti, Pt, Ag, Cr, Cu, Al, and the combination thereof; the metal layer (5) is formed by physical vapor deposition, chemical vapor deposition, vacuum evaporation, plating, chemical plating or the combination thereof, wherein the metal layer (5) has a thickness of from 0.1 nm to 1,000 nm; the photoresist patte rn (6) in the step 3) is a desired pattern formed by lithography, and the pattern is a designed active region of graphene transistor; the exposed metal in the step 4) is removed by hydrofluoric acid, aqua regia, the mixed solution of potassium iodide and iodine, the mixed solution of ammonia and hydrogen peroxide, boric acid solution, hydrochloric acid solution or the mixed solution of nitric acid and acetic acid, leaving a metal layer on the active region of graphene transistor; the exposed graphene layer in the step 5) is removed by oxygen plasma etching or dry etching.
The method of claim 1, wherein the metal electrodes of the source electrode (7), gate electrode (8), and drain electrode (9) in the step 6) are respectively made of one or more selected from the group consisting of 14 ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, nickel, tungsten, copper, cobalt, and iron, and the metal electrodes have a thickness of from 0.1 nm to 1,000 nm respectively; the photoresist gate mask pattern in the step 7) has one or more layers, wherein the gate pattern is a straight gate, T gate, T-T gate, Y gate, r gate, or V gate; the exposed metal in the step 8) is removed by hydrofluoric acid, aqua regia, the mixed solution of potassium iodide and iodine, the mixed solution of ammonia and hydrogen peroxide, boric acid solution, hydrochloric acid solution, or the mixed solution of nitric acid and acetic acid.
The method of claim 1, wherein the seed layer of the gate dielectric in the step 9) is formed from an absorbed NO2, Polyvinyl alcohol, Anthracenemethanol or metal oxide, wherein the seed layer has a thickness of less than 10 nm; the gate dielectric (12) in the step 10) is formed on the seed layer (11), wherein the gate dielectric is selected from the group consisting of HfO 2, ZrO2, La₂ O 3, A 120 3, T 1O 2, SrTiO3, LaAlO3, Y₂ 03, HfO XNy, ZrO XNy, La₂ OxNy, A₁₂ OXNy, TiO XNy, SrTiO XNy, LaAlO XNy, Y 2OXNy, silicate and the combination thereof, wherein x = 0.5 to 3, Y = 0 to 2; the gate dielectric layer in the step 10) is formed by physical vapor deposition, chemical vapor deposition, atomic layer vapor deposition, molecular beam epitaxy, Sol-Gel process or the combination thereof.
The method of claim 1, wherein the step 6 is carried out after the step 11) or step 12).
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (self-aligned)
Materials described outside the worked examples.
graphene
C
metal layer (sacrificial/masking)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–1000 nm | — |
Thickness |
Patent
Atlas literature
Patent
US 9,349,825Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for producing a graphene transistor based on self-aligning technology comprising: 1) forming a graphene layer (4) on a substrate (1); 2) depositing a metal layer (5) on the graphene layer (4); 3) covering a des i red region on the metal layer (5) with a photoresist pattern (6); 4) using the photoresist pattern (6) as a mask to remove an exposed metal; 5) using the photoresist pattern (6) as a mask to etch away an exposed graphene prior to removing the photoresist; 6) forming metal electrodes of a source electrode (7), gate electrode (8) and drain electrode (9), wherein the source electrode (7) and drain electrode (9) are connected with a metal of the active region; 7) forming a gate mask patte rn (10) from a photoresist between the source electrode (7) and the drain electrode (9); 8) using the gate pattern of photoresist as a mask to remove an exposed metal; 9) forming a gate dielectric seed layer (11) on an exposed graphene layer (4) by using the gate pattern of photoresist as a mask; 10) forming a gate dielectric (12) on the gate dielectric seed layer; 11) forming a gate metal (13) on the gate dielectric and removing the photoresist.
The method of claim 1, wherein the method further comprises the following step 12): forming a self-aligning metal (14) by means of the mask function of the gate metal with self-aligning, wherein the gate cap of the gate metal has a larger width than that of the gate base.
The method of claim 1, wherein the substrate is an insulation layer 13 (2) made of SixOy, Si XNy, BN, A lXOy, Hf XOy, A lXNy, SiC, Si, Sapphire, glass, polyethylene terephthalate material, polyi mi de, polydimethyl siloxane or the combination thereof, wherein x = 0.5 to 3, Y = 0 to 2.
The method of claim 1, wherein the graphene layer (4) in the step 1) is deposited directly or epitaxially grow on the substrate (1) or another material, and it is transferred onto the substrate by peeling off, wherein the graphene layer (4) has one or more layers.
The method of claim 1, wherein the metal layer (5) in the step 2) is a metal that can be corroded by a chemical solution, which is selected from the group consisting of Au, Ti, Pt, Ag, Cr, Cu, Al, and the combination thereof; the metal layer (5) is formed by physical vapor deposition, chemical vapor deposition, vacuum evaporation, plating, chemical plating or the combination thereof, wherein the metal layer (5) has a thickness of from 0.1 nm to 1,000 nm; the photoresist patte rn (6) in the step 3) is a desired pattern formed by lithography, and the pattern is a designed active region of graphene transistor; the exposed metal in the step 4) is removed by hydrofluoric acid, aqua regia, the mixed solution of potassium iodide and iodine, the mixed solution of ammonia and hydrogen peroxide, boric acid solution, hydrochloric acid solution or the mixed solution of nitric acid and acetic acid, leaving a metal layer on the active region of graphene transistor; the exposed graphene layer in the step 5) is removed by oxygen plasma etching or dry etching.
The method of claim 1, wherein the metal electrodes of the source electrode (7), gate electrode (8), and drain electrode (9) in the step 6) are respectively made of one or more selected from the group consisting of 14 ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, nickel, tungsten, copper, cobalt, and iron, and the metal electrodes have a thickness of from 0.1 nm to 1,000 nm respectively; the photoresist gate mask pattern in the step 7) has one or more layers, wherein the gate pattern is a straight gate, T gate, T-T gate, Y gate, r gate, or V gate; the exposed metal in the step 8) is removed by hydrofluoric acid, aqua regia, the mixed solution of potassium iodide and iodine, the mixed solution of ammonia and hydrogen peroxide, boric acid solution, hydrochloric acid solution, or the mixed solution of nitric acid and acetic acid.
The method of claim 1, wherein the seed layer of the gate dielectric in the step 9) is formed from an absorbed NO2, Polyvinyl alcohol, Anthracenemethanol or metal oxide, wherein the seed layer has a thickness of less than 10 nm; the gate dielectric (12) in the step 10) is formed on the seed layer (11), wherein the gate dielectric is selected from the group consisting of HfO 2, ZrO2, La₂ O 3, A 120 3, T 1O 2, SrTiO3, LaAlO3, Y₂ 03, HfO XNy, ZrO XNy, La₂ OxNy, A₁₂ OXNy, TiO XNy, SrTiO XNy, LaAlO XNy, Y 2OXNy, silicate and the combination thereof, wherein x = 0.5 to 3, Y = 0 to 2; the gate dielectric layer in the step 10) is formed by physical vapor deposition, chemical vapor deposition, atomic layer vapor deposition, molecular beam epitaxy, Sol-Gel process or the combination thereof.
The method of claim 1, wherein the step 6 is carried out after the step 11) or step 12).
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (self-aligned)
Materials described outside the worked examples.
graphene
C
metal layer (sacrificial/masking)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–1000 nm | — |
Thickness |
Patent
Atlas literature
Patent
US 9,349,825Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for producing a graphene transistor based on self-aligning technology comprising: 1) forming a graphene layer (4) on a substrate (1); 2) depositing a metal layer (5) on the graphene layer (4); 3) covering a des i red region on the metal layer (5) with a photoresist pattern (6); 4) using the photoresist pattern (6) as a mask to remove an exposed metal; 5) using the photoresist pattern (6) as a mask to etch away an exposed graphene prior to removing the photoresist; 6) forming metal electrodes of a source electrode (7), gate electrode (8) and drain electrode (9), wherein the source electrode (7) and drain electrode (9) are connected with a metal of the active region; 7) forming a gate mask patte rn (10) from a photoresist between the source electrode (7) and the drain electrode (9); 8) using the gate pattern of photoresist as a mask to remove an exposed metal; 9) forming a gate dielectric seed layer (11) on an exposed graphene layer (4) by using the gate pattern of photoresist as a mask; 10) forming a gate dielectric (12) on the gate dielectric seed layer; 11) forming a gate metal (13) on the gate dielectric and removing the photoresist.
The method of claim 1, wherein the method further comprises the following step 12): forming a self-aligning metal (14) by means of the mask function of the gate metal with self-aligning, wherein the gate cap of the gate metal has a larger width than that of the gate base.
The method of claim 1, wherein the substrate is an insulation layer 13 (2) made of SixOy, Si XNy, BN, A lXOy, Hf XOy, A lXNy, SiC, Si, Sapphire, glass, polyethylene terephthalate material, polyi mi de, polydimethyl siloxane or the combination thereof, wherein x = 0.5 to 3, Y = 0 to 2.
The method of claim 1, wherein the graphene layer (4) in the step 1) is deposited directly or epitaxially grow on the substrate (1) or another material, and it is transferred onto the substrate by peeling off, wherein the graphene layer (4) has one or more layers.
The method of claim 1, wherein the metal layer (5) in the step 2) is a metal that can be corroded by a chemical solution, which is selected from the group consisting of Au, Ti, Pt, Ag, Cr, Cu, Al, and the combination thereof; the metal layer (5) is formed by physical vapor deposition, chemical vapor deposition, vacuum evaporation, plating, chemical plating or the combination thereof, wherein the metal layer (5) has a thickness of from 0.1 nm to 1,000 nm; the photoresist patte rn (6) in the step 3) is a desired pattern formed by lithography, and the pattern is a designed active region of graphene transistor; the exposed metal in the step 4) is removed by hydrofluoric acid, aqua regia, the mixed solution of potassium iodide and iodine, the mixed solution of ammonia and hydrogen peroxide, boric acid solution, hydrochloric acid solution or the mixed solution of nitric acid and acetic acid, leaving a metal layer on the active region of graphene transistor; the exposed graphene layer in the step 5) is removed by oxygen plasma etching or dry etching.
The method of claim 1, wherein the metal electrodes of the source electrode (7), gate electrode (8), and drain electrode (9) in the step 6) are respectively made of one or more selected from the group consisting of 14 ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, nickel, tungsten, copper, cobalt, and iron, and the metal electrodes have a thickness of from 0.1 nm to 1,000 nm respectively; the photoresist gate mask pattern in the step 7) has one or more layers, wherein the gate pattern is a straight gate, T gate, T-T gate, Y gate, r gate, or V gate; the exposed metal in the step 8) is removed by hydrofluoric acid, aqua regia, the mixed solution of potassium iodide and iodine, the mixed solution of ammonia and hydrogen peroxide, boric acid solution, hydrochloric acid solution, or the mixed solution of nitric acid and acetic acid.
The method of claim 1, wherein the seed layer of the gate dielectric in the step 9) is formed from an absorbed NO2, Polyvinyl alcohol, Anthracenemethanol or metal oxide, wherein the seed layer has a thickness of less than 10 nm; the gate dielectric (12) in the step 10) is formed on the seed layer (11), wherein the gate dielectric is selected from the group consisting of HfO 2, ZrO2, La₂ O 3, A 120 3, T 1O 2, SrTiO3, LaAlO3, Y₂ 03, HfO XNy, ZrO XNy, La₂ OxNy, A₁₂ OXNy, TiO XNy, SrTiO XNy, LaAlO XNy, Y 2OXNy, silicate and the combination thereof, wherein x = 0.5 to 3, Y = 0 to 2; the gate dielectric layer in the step 10) is formed by physical vapor deposition, chemical vapor deposition, atomic layer vapor deposition, molecular beam epitaxy, Sol-Gel process or the combination thereof.
The method of claim 1, wherein the step 6 is carried out after the step 11) or step 12).
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (self-aligned)
Materials described outside the worked examples.
graphene
C
metal layer (sacrificial/masking)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–1000 nm | — |
Thickness |
Patent
Atlas literature
Patent
US 9,349,825Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for producing a graphene transistor based on self-aligning technology comprising: 1) forming a graphene layer (4) on a substrate (1); 2) depositing a metal layer (5) on the graphene layer (4); 3) covering a des i red region on the metal layer (5) with a photoresist pattern (6); 4) using the photoresist pattern (6) as a mask to remove an exposed metal; 5) using the photoresist pattern (6) as a mask to etch away an exposed graphene prior to removing the photoresist; 6) forming metal electrodes of a source electrode (7), gate electrode (8) and drain electrode (9), wherein the source electrode (7) and drain electrode (9) are connected with a metal of the active region; 7) forming a gate mask patte rn (10) from a photoresist between the source electrode (7) and the drain electrode (9); 8) using the gate pattern of photoresist as a mask to remove an exposed metal; 9) forming a gate dielectric seed layer (11) on an exposed graphene layer (4) by using the gate pattern of photoresist as a mask; 10) forming a gate dielectric (12) on the gate dielectric seed layer; 11) forming a gate metal (13) on the gate dielectric and removing the photoresist.
The method of claim 1, wherein the method further comprises the following step 12): forming a self-aligning metal (14) by means of the mask function of the gate metal with self-aligning, wherein the gate cap of the gate metal has a larger width than that of the gate base.
The method of claim 1, wherein the substrate is an insulation layer 13 (2) made of SixOy, Si XNy, BN, A lXOy, Hf XOy, A lXNy, SiC, Si, Sapphire, glass, polyethylene terephthalate material, polyi mi de, polydimethyl siloxane or the combination thereof, wherein x = 0.5 to 3, Y = 0 to 2.
The method of claim 1, wherein the graphene layer (4) in the step 1) is deposited directly or epitaxially grow on the substrate (1) or another material, and it is transferred onto the substrate by peeling off, wherein the graphene layer (4) has one or more layers.
The method of claim 1, wherein the metal layer (5) in the step 2) is a metal that can be corroded by a chemical solution, which is selected from the group consisting of Au, Ti, Pt, Ag, Cr, Cu, Al, and the combination thereof; the metal layer (5) is formed by physical vapor deposition, chemical vapor deposition, vacuum evaporation, plating, chemical plating or the combination thereof, wherein the metal layer (5) has a thickness of from 0.1 nm to 1,000 nm; the photoresist patte rn (6) in the step 3) is a desired pattern formed by lithography, and the pattern is a designed active region of graphene transistor; the exposed metal in the step 4) is removed by hydrofluoric acid, aqua regia, the mixed solution of potassium iodide and iodine, the mixed solution of ammonia and hydrogen peroxide, boric acid solution, hydrochloric acid solution or the mixed solution of nitric acid and acetic acid, leaving a metal layer on the active region of graphene transistor; the exposed graphene layer in the step 5) is removed by oxygen plasma etching or dry etching.
The method of claim 1, wherein the metal electrodes of the source electrode (7), gate electrode (8), and drain electrode (9) in the step 6) are respectively made of one or more selected from the group consisting of 14 ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, nickel, tungsten, copper, cobalt, and iron, and the metal electrodes have a thickness of from 0.1 nm to 1,000 nm respectively; the photoresist gate mask pattern in the step 7) has one or more layers, wherein the gate pattern is a straight gate, T gate, T-T gate, Y gate, r gate, or V gate; the exposed metal in the step 8) is removed by hydrofluoric acid, aqua regia, the mixed solution of potassium iodide and iodine, the mixed solution of ammonia and hydrogen peroxide, boric acid solution, hydrochloric acid solution, or the mixed solution of nitric acid and acetic acid.
The method of claim 1, wherein the seed layer of the gate dielectric in the step 9) is formed from an absorbed NO2, Polyvinyl alcohol, Anthracenemethanol or metal oxide, wherein the seed layer has a thickness of less than 10 nm; the gate dielectric (12) in the step 10) is formed on the seed layer (11), wherein the gate dielectric is selected from the group consisting of HfO 2, ZrO2, La₂ O 3, A 120 3, T 1O 2, SrTiO3, LaAlO3, Y₂ 03, HfO XNy, ZrO XNy, La₂ OxNy, A₁₂ OXNy, TiO XNy, SrTiO XNy, LaAlO XNy, Y 2OXNy, silicate and the combination thereof, wherein x = 0.5 to 3, Y = 0 to 2; the gate dielectric layer in the step 10) is formed by physical vapor deposition, chemical vapor deposition, atomic layer vapor deposition, molecular beam epitaxy, Sol-Gel process or the combination thereof.
The method of claim 1, wherein the step 6 is carried out after the step 11) or step 12).
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (self-aligned)
Materials described outside the worked examples.
graphene
C
metal layer (sacrificial/masking)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–1000 nm | — |
Thickness |
metal electrodes (source, gate, drain)
gate dielectric seed layer
gate metal
substrate insulation layer
gate dielectric
| ≤ 10 nm |
| — |
metal electrodes (source, gate, drain)
gate dielectric seed layer
gate metal
substrate insulation layer
gate dielectric
| ≤ 10 nm |
| — |
metal electrodes (source, gate, drain)
gate dielectric seed layer
gate metal
substrate insulation layer
gate dielectric
| ≤ 10 nm |
| — |
metal electrodes (source, gate, drain)
gate dielectric seed layer
gate metal
substrate insulation layer
gate dielectric
| ≤ 10 nm |
| — |