Patent
US 11,139,405METHOD FOR FABRICATING NANOPILLAR SOLAR CELL USING GRAPHENE
Ming Zhou
Semiconductor Manufacturing International (Shanghai) Corporation·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,139,405Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified flow chart of a method of manufacturing a semiconductor device 5 according to an embodiment of the present invention; [0030]
FIG. 2B. Preferably, protective layer 204 may be a glass film; more preferably, the protection layer 204 may be a film of silica glass. [0053]
FIG. 3B illustrates a cross sectional view of a graphene layer formed on a plurality of 15 nanopillars according to another embodiment of the present …
FIG. 4C, the plurality of nanopores 402 are filled with a hard mask materia l 403. For example, titanium nitride may be deposited as a hard mask materia l 402 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing a semiconductor device, comprising: providing an initial substrate structure, the initial substrate structure comprising: a conductive layer; a first semiconductor layer on the conductive layer; and a second semiconductor layer on the first semiconductor layer, the first semiconductor layer and the second semiconductor layer having different conductivity types such that a homogeneous PN junction being formed at an interface between the first semiconductor layer and the second semiconductor layer; forming an aluminum layer on the second semiconductor layer; oxidizing an upper portion of the aluminum layer to form an aluminum oxide layer by an anodic oxidation process in which a plurality of nanopores are formed in the aluminum oxide layer, the plurality of nanopores extending through the aluminum oxide layer into the aluminum layer, but not passing through the aluminum layer; filling the plurality of nanopores with a hard mask material; using the hard mask material in the plurality of nanopores as an etch mask, sequentially etching the aluminum oxide layer, the aluminum layer, the second semiconductor layer, and a portion of a top portion of the first semiconductor layer to form a plurality of nanopillars spaced apart from each other on a bottom portion of the first semiconductor layer, wherein the plurality of nanopillars are formed by a remaining portion of the top portion of the first semiconductor layer and a remaining portion of the second semiconductor layer; removing the hard mask material, the aluminum oxide layer, and the aluminum layer; and forming a graphene layer overlying the plurality of nanopillars, the graphene layer being connected to each of the plurality of nanopillars. Currently amended
(Withdrawn-Previously Presented) The method according to claim 1, further comprising removing the hard mask material and the aluminum oxide layer, wherein the graphene layer is in contact with the aluminum layer. Withdrawn
The method according to claim 1, wherein said initial substrate structure further comprises a substrate, the conductive layer being disposed on the substrate. Previously presented
The method of claim 1, wherein the bottom portion of the first semiconductor layer forms a third semiconductor layer disposed on the conductive layer and the remaining portion of the second semiconductor layer and the remaining portion of the top portion of the first semiconductor layer have a same width, the third semiconductor layer comprising a same material as the first semiconductor layer, the plurality of nanopillars being positioned over the third semiconductor layer. Previously presented
The method as claimed in claim 1, wherein the graphene layer is in contact with the second semiconductor layer. Previously presented
The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer comprise silicon; and sequentially etching comprises: using a Cl (chlorine) ion containing plasma, etching the aluminum oxide layer and the aluminum layer with the second semiconductor layer as a plasma etching stop layer; using an F (florine) ion containing plasma, etching the second semiconductor layer and the at least one portion of the first semiconductor layer. Previously presented
The method according to claim 1, wherein the anodic oxidation process is carried out with a voltage of 0-100 V utilizing an electrolyte comprising neutral ammonium pentaborate and ammonium adipate, or an electrolyte comprising phosphoric acid and oxalic acid electrolyte, or a combination of both electrolytes. Previously presented
The method according to claim 1, further comprising: after removing the hard mask material, cleaning a surface of the aluminum layer in the plurality of nanopillars. Previously presented
The method according to claim 1, wherein a transverse dimension of the plurality of nanopores is 5-5000 nm. Previously presented
The method according to claim 1, wherein a transverse dimension of the plurality of nanopillars is 5-5000 nm. Previously presented
The method according to claim 1, wherein forming the graphene layer comprises: forming the graphene layer on a metal substrate; and transferring the graphene layer over the plurality of nanopillars. Previously presented
The method according to claim 1, further comprising: forming a protective layer on the graphene layer. Original
The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed by a same material. Previously presented
(Withdrawn-Previously Presented) The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed by different materials. Withdrawn
The method according to claim 1, after filling the plurality of nanopores with the hard mask material, further comprising: planarizing the hard mask material until a surface of the hard mask material is flush with a surface of the plurality of nanopores. Previously presented
- 22. Canceled
Canceled
Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
nanopillar solar cell
Materials described outside the worked examples.
graphene
semiconductor (first and second semiconductor layers)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 700–1000 °C | — |
Thickness |
Patent
Atlas literature
Patent
US 11,139,405Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified flow chart of a method of manufacturing a semiconductor device 5 according to an embodiment of the present invention; [0030]
FIG. 2B. Preferably, protective layer 204 may be a glass film; more preferably, the protection layer 204 may be a film of silica glass. [0053]
FIG. 3B illustrates a cross sectional view of a graphene layer formed on a plurality of 15 nanopillars according to another embodiment of the present …
FIG. 4C, the plurality of nanopores 402 are filled with a hard mask materia l 403. For example, titanium nitride may be deposited as a hard mask materia l 402 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing a semiconductor device, comprising: providing an initial substrate structure, the initial substrate structure comprising: a conductive layer; a first semiconductor layer on the conductive layer; and a second semiconductor layer on the first semiconductor layer, the first semiconductor layer and the second semiconductor layer having different conductivity types such that a homogeneous PN junction being formed at an interface between the first semiconductor layer and the second semiconductor layer; forming an aluminum layer on the second semiconductor layer; oxidizing an upper portion of the aluminum layer to form an aluminum oxide layer by an anodic oxidation process in which a plurality of nanopores are formed in the aluminum oxide layer, the plurality of nanopores extending through the aluminum oxide layer into the aluminum layer, but not passing through the aluminum layer; filling the plurality of nanopores with a hard mask material; using the hard mask material in the plurality of nanopores as an etch mask, sequentially etching the aluminum oxide layer, the aluminum layer, the second semiconductor layer, and a portion of a top portion of the first semiconductor layer to form a plurality of nanopillars spaced apart from each other on a bottom portion of the first semiconductor layer, wherein the plurality of nanopillars are formed by a remaining portion of the top portion of the first semiconductor layer and a remaining portion of the second semiconductor layer; removing the hard mask material, the aluminum oxide layer, and the aluminum layer; and forming a graphene layer overlying the plurality of nanopillars, the graphene layer being connected to each of the plurality of nanopillars. Currently amended
(Withdrawn-Previously Presented) The method according to claim 1, further comprising removing the hard mask material and the aluminum oxide layer, wherein the graphene layer is in contact with the aluminum layer. Withdrawn
The method according to claim 1, wherein said initial substrate structure further comprises a substrate, the conductive layer being disposed on the substrate. Previously presented
The method of claim 1, wherein the bottom portion of the first semiconductor layer forms a third semiconductor layer disposed on the conductive layer and the remaining portion of the second semiconductor layer and the remaining portion of the top portion of the first semiconductor layer have a same width, the third semiconductor layer comprising a same material as the first semiconductor layer, the plurality of nanopillars being positioned over the third semiconductor layer. Previously presented
The method as claimed in claim 1, wherein the graphene layer is in contact with the second semiconductor layer. Previously presented
The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer comprise silicon; and sequentially etching comprises: using a Cl (chlorine) ion containing plasma, etching the aluminum oxide layer and the aluminum layer with the second semiconductor layer as a plasma etching stop layer; using an F (florine) ion containing plasma, etching the second semiconductor layer and the at least one portion of the first semiconductor layer. Previously presented
The method according to claim 1, wherein the anodic oxidation process is carried out with a voltage of 0-100 V utilizing an electrolyte comprising neutral ammonium pentaborate and ammonium adipate, or an electrolyte comprising phosphoric acid and oxalic acid electrolyte, or a combination of both electrolytes. Previously presented
The method according to claim 1, further comprising: after removing the hard mask material, cleaning a surface of the aluminum layer in the plurality of nanopillars. Previously presented
The method according to claim 1, wherein a transverse dimension of the plurality of nanopores is 5-5000 nm. Previously presented
The method according to claim 1, wherein a transverse dimension of the plurality of nanopillars is 5-5000 nm. Previously presented
The method according to claim 1, wherein forming the graphene layer comprises: forming the graphene layer on a metal substrate; and transferring the graphene layer over the plurality of nanopillars. Previously presented
The method according to claim 1, further comprising: forming a protective layer on the graphene layer. Original
The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed by a same material. Previously presented
(Withdrawn-Previously Presented) The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed by different materials. Withdrawn
The method according to claim 1, after filling the plurality of nanopores with the hard mask material, further comprising: planarizing the hard mask material until a surface of the hard mask material is flush with a surface of the plurality of nanopores. Previously presented
- 22. Canceled
Canceled
Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
nanopillar solar cell
Materials described outside the worked examples.
graphene
semiconductor (first and second semiconductor layers)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 700–1000 °C | — |
Thickness |
Patent
Atlas literature
Patent
US 11,139,405Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified flow chart of a method of manufacturing a semiconductor device 5 according to an embodiment of the present invention; [0030]
FIG. 2B. Preferably, protective layer 204 may be a glass film; more preferably, the protection layer 204 may be a film of silica glass. [0053]
FIG. 3B illustrates a cross sectional view of a graphene layer formed on a plurality of 15 nanopillars according to another embodiment of the present …
FIG. 4C, the plurality of nanopores 402 are filled with a hard mask materia l 403. For example, titanium nitride may be deposited as a hard mask materia l 402 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing a semiconductor device, comprising: providing an initial substrate structure, the initial substrate structure comprising: a conductive layer; a first semiconductor layer on the conductive layer; and a second semiconductor layer on the first semiconductor layer, the first semiconductor layer and the second semiconductor layer having different conductivity types such that a homogeneous PN junction being formed at an interface between the first semiconductor layer and the second semiconductor layer; forming an aluminum layer on the second semiconductor layer; oxidizing an upper portion of the aluminum layer to form an aluminum oxide layer by an anodic oxidation process in which a plurality of nanopores are formed in the aluminum oxide layer, the plurality of nanopores extending through the aluminum oxide layer into the aluminum layer, but not passing through the aluminum layer; filling the plurality of nanopores with a hard mask material; using the hard mask material in the plurality of nanopores as an etch mask, sequentially etching the aluminum oxide layer, the aluminum layer, the second semiconductor layer, and a portion of a top portion of the first semiconductor layer to form a plurality of nanopillars spaced apart from each other on a bottom portion of the first semiconductor layer, wherein the plurality of nanopillars are formed by a remaining portion of the top portion of the first semiconductor layer and a remaining portion of the second semiconductor layer; removing the hard mask material, the aluminum oxide layer, and the aluminum layer; and forming a graphene layer overlying the plurality of nanopillars, the graphene layer being connected to each of the plurality of nanopillars. Currently amended
(Withdrawn-Previously Presented) The method according to claim 1, further comprising removing the hard mask material and the aluminum oxide layer, wherein the graphene layer is in contact with the aluminum layer. Withdrawn
The method according to claim 1, wherein said initial substrate structure further comprises a substrate, the conductive layer being disposed on the substrate. Previously presented
The method of claim 1, wherein the bottom portion of the first semiconductor layer forms a third semiconductor layer disposed on the conductive layer and the remaining portion of the second semiconductor layer and the remaining portion of the top portion of the first semiconductor layer have a same width, the third semiconductor layer comprising a same material as the first semiconductor layer, the plurality of nanopillars being positioned over the third semiconductor layer. Previously presented
The method as claimed in claim 1, wherein the graphene layer is in contact with the second semiconductor layer. Previously presented
The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer comprise silicon; and sequentially etching comprises: using a Cl (chlorine) ion containing plasma, etching the aluminum oxide layer and the aluminum layer with the second semiconductor layer as a plasma etching stop layer; using an F (florine) ion containing plasma, etching the second semiconductor layer and the at least one portion of the first semiconductor layer. Previously presented
The method according to claim 1, wherein the anodic oxidation process is carried out with a voltage of 0-100 V utilizing an electrolyte comprising neutral ammonium pentaborate and ammonium adipate, or an electrolyte comprising phosphoric acid and oxalic acid electrolyte, or a combination of both electrolytes. Previously presented
The method according to claim 1, further comprising: after removing the hard mask material, cleaning a surface of the aluminum layer in the plurality of nanopillars. Previously presented
The method according to claim 1, wherein a transverse dimension of the plurality of nanopores is 5-5000 nm. Previously presented
The method according to claim 1, wherein a transverse dimension of the plurality of nanopillars is 5-5000 nm. Previously presented
The method according to claim 1, wherein forming the graphene layer comprises: forming the graphene layer on a metal substrate; and transferring the graphene layer over the plurality of nanopillars. Previously presented
The method according to claim 1, further comprising: forming a protective layer on the graphene layer. Original
The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed by a same material. Previously presented
(Withdrawn-Previously Presented) The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed by different materials. Withdrawn
The method according to claim 1, after filling the plurality of nanopores with the hard mask material, further comprising: planarizing the hard mask material until a surface of the hard mask material is flush with a surface of the plurality of nanopores. Previously presented
- 22. Canceled
Canceled
Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
nanopillar solar cell
Materials described outside the worked examples.
graphene
semiconductor (first and second semiconductor layers)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 700–1000 °C | — |
Thickness |
Patent
Atlas literature
Patent
US 11,139,405Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified flow chart of a method of manufacturing a semiconductor device 5 according to an embodiment of the present invention; [0030]
FIG. 2B. Preferably, protective layer 204 may be a glass film; more preferably, the protection layer 204 may be a film of silica glass. [0053]
FIG. 3B illustrates a cross sectional view of a graphene layer formed on a plurality of 15 nanopillars according to another embodiment of the present …
FIG. 4C, the plurality of nanopores 402 are filled with a hard mask materia l 403. For example, titanium nitride may be deposited as a hard mask materia l 402 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing a semiconductor device, comprising: providing an initial substrate structure, the initial substrate structure comprising: a conductive layer; a first semiconductor layer on the conductive layer; and a second semiconductor layer on the first semiconductor layer, the first semiconductor layer and the second semiconductor layer having different conductivity types such that a homogeneous PN junction being formed at an interface between the first semiconductor layer and the second semiconductor layer; forming an aluminum layer on the second semiconductor layer; oxidizing an upper portion of the aluminum layer to form an aluminum oxide layer by an anodic oxidation process in which a plurality of nanopores are formed in the aluminum oxide layer, the plurality of nanopores extending through the aluminum oxide layer into the aluminum layer, but not passing through the aluminum layer; filling the plurality of nanopores with a hard mask material; using the hard mask material in the plurality of nanopores as an etch mask, sequentially etching the aluminum oxide layer, the aluminum layer, the second semiconductor layer, and a portion of a top portion of the first semiconductor layer to form a plurality of nanopillars spaced apart from each other on a bottom portion of the first semiconductor layer, wherein the plurality of nanopillars are formed by a remaining portion of the top portion of the first semiconductor layer and a remaining portion of the second semiconductor layer; removing the hard mask material, the aluminum oxide layer, and the aluminum layer; and forming a graphene layer overlying the plurality of nanopillars, the graphene layer being connected to each of the plurality of nanopillars. Currently amended
(Withdrawn-Previously Presented) The method according to claim 1, further comprising removing the hard mask material and the aluminum oxide layer, wherein the graphene layer is in contact with the aluminum layer. Withdrawn
The method according to claim 1, wherein said initial substrate structure further comprises a substrate, the conductive layer being disposed on the substrate. Previously presented
The method of claim 1, wherein the bottom portion of the first semiconductor layer forms a third semiconductor layer disposed on the conductive layer and the remaining portion of the second semiconductor layer and the remaining portion of the top portion of the first semiconductor layer have a same width, the third semiconductor layer comprising a same material as the first semiconductor layer, the plurality of nanopillars being positioned over the third semiconductor layer. Previously presented
The method as claimed in claim 1, wherein the graphene layer is in contact with the second semiconductor layer. Previously presented
The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer comprise silicon; and sequentially etching comprises: using a Cl (chlorine) ion containing plasma, etching the aluminum oxide layer and the aluminum layer with the second semiconductor layer as a plasma etching stop layer; using an F (florine) ion containing plasma, etching the second semiconductor layer and the at least one portion of the first semiconductor layer. Previously presented
The method according to claim 1, wherein the anodic oxidation process is carried out with a voltage of 0-100 V utilizing an electrolyte comprising neutral ammonium pentaborate and ammonium adipate, or an electrolyte comprising phosphoric acid and oxalic acid electrolyte, or a combination of both electrolytes. Previously presented
The method according to claim 1, further comprising: after removing the hard mask material, cleaning a surface of the aluminum layer in the plurality of nanopillars. Previously presented
The method according to claim 1, wherein a transverse dimension of the plurality of nanopores is 5-5000 nm. Previously presented
The method according to claim 1, wherein a transverse dimension of the plurality of nanopillars is 5-5000 nm. Previously presented
The method according to claim 1, wherein forming the graphene layer comprises: forming the graphene layer on a metal substrate; and transferring the graphene layer over the plurality of nanopillars. Previously presented
The method according to claim 1, further comprising: forming a protective layer on the graphene layer. Original
The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed by a same material. Previously presented
(Withdrawn-Previously Presented) The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed by different materials. Withdrawn
The method according to claim 1, after filling the plurality of nanopores with the hard mask material, further comprising: planarizing the hard mask material until a surface of the hard mask material is flush with a surface of the plurality of nanopores. Previously presented
- 22. Canceled
Canceled
Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
nanopillar solar cell
Materials described outside the worked examples.
graphene
semiconductor (first and second semiconductor layers)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 700–1000 °C | — |
Thickness |
silicon
Si
aluminum oxide
Al₂O₃
aluminum
Al
titanium nitride
TiN
protective layer
sodium carbonate
Na₂CO₃
triethanolamine
conductive layer
| 5–5000 nm |
| — |
Voltage | 0–100 V | — |
silicon
Si
aluminum oxide
Al₂O₃
aluminum
Al
titanium nitride
TiN
protective layer
sodium carbonate
Na₂CO₃
triethanolamine
conductive layer
| 5–5000 nm |
| — |
Voltage | 0–100 V | — |
silicon
Si
aluminum oxide
Al₂O₃
aluminum
Al
titanium nitride
TiN
protective layer
sodium carbonate
Na₂CO₃
triethanolamine
conductive layer
| 5–5000 nm |
| — |
Voltage | 0–100 V | — |
silicon
Si
aluminum oxide
Al₂O₃
aluminum
Al
titanium nitride
TiN
protective layer
sodium carbonate
Na₂CO₃
triethanolamine
conductive layer
| 5–5000 nm |
| — |
Voltage | 0–100 V | — |