Patent
US 9,064,777GRAPHENE SWITCHING DEVICE HAVING TUNABLE BARRIER
Jin-Seong HEO
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,064,777Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a graphene switching device including a tunable barrier according to example embodiments; [0041]
FIGS. 2A through 2D are energy band diagrams for explaining an operation of the graphene switching device of
FIG. 3 is an I-V characteristic curve of an n-type graphene switching device according to example embodiments; [0043]
FIG. 4 is an I-V characteristic curve of a p-type graphene switching device according to example embodiments; [0044]
FIG. 5 is a schematic cross-sectional view of a graphene switching device including a tunable barrier according to example embodiments; and [0045]
FIG. 6 is a schematic cross- sectional view of a graphene switching device including a tunable barrier according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
- 8. canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
A graphene switching device having a tunable barrier, comprising: a semiconductor layer configured to form an energy gap between a graphene layer and a first electrode, the first electrode being on a first region of the semiconductor layer, the graphene layer being on the semiconductor layer, the graphene layer having a zero band gap; an insulating layer on a second region of the semiconductor layer, the insulating layer being separated from the first electrode, the graphene layer being between the first electrode and the insulating layer, the graphene layer extending onto the insulating layer; a second electrode on the graphene layer and the second region of the semiconductor layer, the second electrode facing the insulating layer; a gate dielectric on the graphene layer; and a gate electrode on the gate dielectric.
The graphene switching device of claim 9, wherein the semiconductor layer includes one of silicon, germanium, silicon-germanium, a group III -V semiconductor, and a group I I -VI semiconductor.
The graphene switching device of claim 9, wherein the graphene layer is separated from the first electrode.
The graphene switching device of claim 9, wherein a gap between the graphene layer and the first electrode is about 1 nm to about 30 nm.
The graphene switching device of claim 9, wherein the first and second electrodes contain one of metal and polysilicon.
The graphene switching device of claim 9, wherein the graphene switching device is a uni-polar transistor having a polarity that is the same as an impurity type of the semiconductor layer.
The graphene switching device of claim 9, wherein at least a portion of the graphene layer has one to four layers of graphene.
The graphene switching device of claim 9, wherein the first and second electrodes are on a same contiguous portion of the semiconductor layer.
The graphene switching device of claim 9, wherein a bottommost surface of the graphene layer, a bottommost surface of the first electrode, and a bottommost surface of the insulating layer are on an upper surface of the semiconductor layer.
A graphene switching device having a tunable barrier, comprising: a graphene layer including a first surface opposite a second surface; a semiconductor layer containing one of an n-type impurity and a p-type impurity, the semiconductor layer contacting one of a first part of the first surface of the graphene layer and a first part of the second surface of the graphene layer, the graphene layer having a zero band gap; a first electrode contacting the semiconductor layer, the first electrode being separated from the graphene layer, a second electrode contacting a second part of the first surface of the graphene layer; a gate electrode; and a gate dielectric contacting the gate electrode and the graphene layer, the gate dielectric being between the gate electrode and the semiconductor layer.
(Origin al) The graphene switching device of claim 17, wherein the semiconductor layer includes one of silicon, germanium, silicon-germanium, a group III -V semiconductor, and a group I I -VI semiconductor.
The graphene switching device of claim 17, wherein at least one of the first and second electrodes contains one of metal and polysi l icon.
The graphene switching device of claim 17, wherein at least a portion of the graphene layer has a thickness of one to four layers of graphene.
The graphene switching device of claim 17, wherein the graphene switching device is a uni-polar transistor having a polarity that is the same as an impurity type of the semiconductor layer.
The graphene switching device of claim 17, wherein the gate dielectric is on the gate electrode, the graphene layer is on the gate dielectric, the semiconductor layer is on the graphene layer and contacts the first part of the first surface of the graphene layer, the first electrode is on the semiconductor layer, and the second electrode is spaced apart from the semiconductor layer on the first surface of the graphene layer. withdrawn
The graphene switching device of claim 17, wherein the semiconductor layer contacts the first part of the second surface of the graphene layer, the graphene layer is on the semiconductor layer, the first electrode is on the semiconductor layer, the gate dielectric is on the graphene layer, and the gate electrode is on the gate dielectric.
The graphene switching device of claim 17, wherein the graphene layer is configured to function as a pathway for one of electrons and holes flowing through the graphene layer when a gate voltage is applied to the gate electrode.
The graphene switching device of claim 17, further comprising: an insulating layer below the second electrode and the graphene layer, wherein a bottommost surface of the graphene layer, a bottommost surface of the first electrode, and a bottommost surface of the insulating layer are on an upper surface of the semiconductor layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene switching device with tunable barrier (semiconductor-on-graphene topology)
graphene switching device with tunable barrier (graphene two-surface topology)
Materials described outside the worked examples.
graphene
C
semiconductor layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is an I-V characteristic curve of an n-type graphene switching device according to example embodiments; [0043]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness |
Patent
Atlas literature
Patent
US 9,064,777Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a graphene switching device including a tunable barrier according to example embodiments; [0041]
FIGS. 2A through 2D are energy band diagrams for explaining an operation of the graphene switching device of
FIG. 3 is an I-V characteristic curve of an n-type graphene switching device according to example embodiments; [0043]
FIG. 4 is an I-V characteristic curve of a p-type graphene switching device according to example embodiments; [0044]
FIG. 5 is a schematic cross-sectional view of a graphene switching device including a tunable barrier according to example embodiments; and [0045]
FIG. 6 is a schematic cross- sectional view of a graphene switching device including a tunable barrier according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
- 8. canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
A graphene switching device having a tunable barrier, comprising: a semiconductor layer configured to form an energy gap between a graphene layer and a first electrode, the first electrode being on a first region of the semiconductor layer, the graphene layer being on the semiconductor layer, the graphene layer having a zero band gap; an insulating layer on a second region of the semiconductor layer, the insulating layer being separated from the first electrode, the graphene layer being between the first electrode and the insulating layer, the graphene layer extending onto the insulating layer; a second electrode on the graphene layer and the second region of the semiconductor layer, the second electrode facing the insulating layer; a gate dielectric on the graphene layer; and a gate electrode on the gate dielectric.
The graphene switching device of claim 9, wherein the semiconductor layer includes one of silicon, germanium, silicon-germanium, a group III -V semiconductor, and a group I I -VI semiconductor.
The graphene switching device of claim 9, wherein the graphene layer is separated from the first electrode.
The graphene switching device of claim 9, wherein a gap between the graphene layer and the first electrode is about 1 nm to about 30 nm.
The graphene switching device of claim 9, wherein the first and second electrodes contain one of metal and polysilicon.
The graphene switching device of claim 9, wherein the graphene switching device is a uni-polar transistor having a polarity that is the same as an impurity type of the semiconductor layer.
The graphene switching device of claim 9, wherein at least a portion of the graphene layer has one to four layers of graphene.
The graphene switching device of claim 9, wherein the first and second electrodes are on a same contiguous portion of the semiconductor layer.
The graphene switching device of claim 9, wherein a bottommost surface of the graphene layer, a bottommost surface of the first electrode, and a bottommost surface of the insulating layer are on an upper surface of the semiconductor layer.
A graphene switching device having a tunable barrier, comprising: a graphene layer including a first surface opposite a second surface; a semiconductor layer containing one of an n-type impurity and a p-type impurity, the semiconductor layer contacting one of a first part of the first surface of the graphene layer and a first part of the second surface of the graphene layer, the graphene layer having a zero band gap; a first electrode contacting the semiconductor layer, the first electrode being separated from the graphene layer, a second electrode contacting a second part of the first surface of the graphene layer; a gate electrode; and a gate dielectric contacting the gate electrode and the graphene layer, the gate dielectric being between the gate electrode and the semiconductor layer.
(Origin al) The graphene switching device of claim 17, wherein the semiconductor layer includes one of silicon, germanium, silicon-germanium, a group III -V semiconductor, and a group I I -VI semiconductor.
The graphene switching device of claim 17, wherein at least one of the first and second electrodes contains one of metal and polysi l icon.
The graphene switching device of claim 17, wherein at least a portion of the graphene layer has a thickness of one to four layers of graphene.
The graphene switching device of claim 17, wherein the graphene switching device is a uni-polar transistor having a polarity that is the same as an impurity type of the semiconductor layer.
The graphene switching device of claim 17, wherein the gate dielectric is on the gate electrode, the graphene layer is on the gate dielectric, the semiconductor layer is on the graphene layer and contacts the first part of the first surface of the graphene layer, the first electrode is on the semiconductor layer, and the second electrode is spaced apart from the semiconductor layer on the first surface of the graphene layer. withdrawn
The graphene switching device of claim 17, wherein the semiconductor layer contacts the first part of the second surface of the graphene layer, the graphene layer is on the semiconductor layer, the first electrode is on the semiconductor layer, the gate dielectric is on the graphene layer, and the gate electrode is on the gate dielectric.
The graphene switching device of claim 17, wherein the graphene layer is configured to function as a pathway for one of electrons and holes flowing through the graphene layer when a gate voltage is applied to the gate electrode.
The graphene switching device of claim 17, further comprising: an insulating layer below the second electrode and the graphene layer, wherein a bottommost surface of the graphene layer, a bottommost surface of the first electrode, and a bottommost surface of the insulating layer are on an upper surface of the semiconductor layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene switching device with tunable barrier (semiconductor-on-graphene topology)
graphene switching device with tunable barrier (graphene two-surface topology)
Materials described outside the worked examples.
graphene
C
semiconductor layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is an I-V characteristic curve of an n-type graphene switching device according to example embodiments; [0043]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness |
Patent
Atlas literature
Patent
US 9,064,777Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a graphene switching device including a tunable barrier according to example embodiments; [0041]
FIGS. 2A through 2D are energy band diagrams for explaining an operation of the graphene switching device of
FIG. 3 is an I-V characteristic curve of an n-type graphene switching device according to example embodiments; [0043]
FIG. 4 is an I-V characteristic curve of a p-type graphene switching device according to example embodiments; [0044]
FIG. 5 is a schematic cross-sectional view of a graphene switching device including a tunable barrier according to example embodiments; and [0045]
FIG. 6 is a schematic cross- sectional view of a graphene switching device including a tunable barrier according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
- 8. canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
A graphene switching device having a tunable barrier, comprising: a semiconductor layer configured to form an energy gap between a graphene layer and a first electrode, the first electrode being on a first region of the semiconductor layer, the graphene layer being on the semiconductor layer, the graphene layer having a zero band gap; an insulating layer on a second region of the semiconductor layer, the insulating layer being separated from the first electrode, the graphene layer being between the first electrode and the insulating layer, the graphene layer extending onto the insulating layer; a second electrode on the graphene layer and the second region of the semiconductor layer, the second electrode facing the insulating layer; a gate dielectric on the graphene layer; and a gate electrode on the gate dielectric.
The graphene switching device of claim 9, wherein the semiconductor layer includes one of silicon, germanium, silicon-germanium, a group III -V semiconductor, and a group I I -VI semiconductor.
The graphene switching device of claim 9, wherein the graphene layer is separated from the first electrode.
The graphene switching device of claim 9, wherein a gap between the graphene layer and the first electrode is about 1 nm to about 30 nm.
The graphene switching device of claim 9, wherein the first and second electrodes contain one of metal and polysilicon.
The graphene switching device of claim 9, wherein the graphene switching device is a uni-polar transistor having a polarity that is the same as an impurity type of the semiconductor layer.
The graphene switching device of claim 9, wherein at least a portion of the graphene layer has one to four layers of graphene.
The graphene switching device of claim 9, wherein the first and second electrodes are on a same contiguous portion of the semiconductor layer.
The graphene switching device of claim 9, wherein a bottommost surface of the graphene layer, a bottommost surface of the first electrode, and a bottommost surface of the insulating layer are on an upper surface of the semiconductor layer.
A graphene switching device having a tunable barrier, comprising: a graphene layer including a first surface opposite a second surface; a semiconductor layer containing one of an n-type impurity and a p-type impurity, the semiconductor layer contacting one of a first part of the first surface of the graphene layer and a first part of the second surface of the graphene layer, the graphene layer having a zero band gap; a first electrode contacting the semiconductor layer, the first electrode being separated from the graphene layer, a second electrode contacting a second part of the first surface of the graphene layer; a gate electrode; and a gate dielectric contacting the gate electrode and the graphene layer, the gate dielectric being between the gate electrode and the semiconductor layer.
(Origin al) The graphene switching device of claim 17, wherein the semiconductor layer includes one of silicon, germanium, silicon-germanium, a group III -V semiconductor, and a group I I -VI semiconductor.
The graphene switching device of claim 17, wherein at least one of the first and second electrodes contains one of metal and polysi l icon.
The graphene switching device of claim 17, wherein at least a portion of the graphene layer has a thickness of one to four layers of graphene.
The graphene switching device of claim 17, wherein the graphene switching device is a uni-polar transistor having a polarity that is the same as an impurity type of the semiconductor layer.
The graphene switching device of claim 17, wherein the gate dielectric is on the gate electrode, the graphene layer is on the gate dielectric, the semiconductor layer is on the graphene layer and contacts the first part of the first surface of the graphene layer, the first electrode is on the semiconductor layer, and the second electrode is spaced apart from the semiconductor layer on the first surface of the graphene layer. withdrawn
The graphene switching device of claim 17, wherein the semiconductor layer contacts the first part of the second surface of the graphene layer, the graphene layer is on the semiconductor layer, the first electrode is on the semiconductor layer, the gate dielectric is on the graphene layer, and the gate electrode is on the gate dielectric.
The graphene switching device of claim 17, wherein the graphene layer is configured to function as a pathway for one of electrons and holes flowing through the graphene layer when a gate voltage is applied to the gate electrode.
The graphene switching device of claim 17, further comprising: an insulating layer below the second electrode and the graphene layer, wherein a bottommost surface of the graphene layer, a bottommost surface of the first electrode, and a bottommost surface of the insulating layer are on an upper surface of the semiconductor layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene switching device with tunable barrier (semiconductor-on-graphene topology)
graphene switching device with tunable barrier (graphene two-surface topology)
Materials described outside the worked examples.
graphene
C
semiconductor layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is an I-V characteristic curve of an n-type graphene switching device according to example embodiments; [0043]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness |
Patent
Atlas literature
Patent
US 9,064,777Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a graphene switching device including a tunable barrier according to example embodiments; [0041]
FIGS. 2A through 2D are energy band diagrams for explaining an operation of the graphene switching device of
FIG. 3 is an I-V characteristic curve of an n-type graphene switching device according to example embodiments; [0043]
FIG. 4 is an I-V characteristic curve of a p-type graphene switching device according to example embodiments; [0044]
FIG. 5 is a schematic cross-sectional view of a graphene switching device including a tunable barrier according to example embodiments; and [0045]
FIG. 6 is a schematic cross- sectional view of a graphene switching device including a tunable barrier according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
- 8. canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
A graphene switching device having a tunable barrier, comprising: a semiconductor layer configured to form an energy gap between a graphene layer and a first electrode, the first electrode being on a first region of the semiconductor layer, the graphene layer being on the semiconductor layer, the graphene layer having a zero band gap; an insulating layer on a second region of the semiconductor layer, the insulating layer being separated from the first electrode, the graphene layer being between the first electrode and the insulating layer, the graphene layer extending onto the insulating layer; a second electrode on the graphene layer and the second region of the semiconductor layer, the second electrode facing the insulating layer; a gate dielectric on the graphene layer; and a gate electrode on the gate dielectric.
The graphene switching device of claim 9, wherein the semiconductor layer includes one of silicon, germanium, silicon-germanium, a group III -V semiconductor, and a group I I -VI semiconductor.
The graphene switching device of claim 9, wherein the graphene layer is separated from the first electrode.
The graphene switching device of claim 9, wherein a gap between the graphene layer and the first electrode is about 1 nm to about 30 nm.
The graphene switching device of claim 9, wherein the first and second electrodes contain one of metal and polysilicon.
The graphene switching device of claim 9, wherein the graphene switching device is a uni-polar transistor having a polarity that is the same as an impurity type of the semiconductor layer.
The graphene switching device of claim 9, wherein at least a portion of the graphene layer has one to four layers of graphene.
The graphene switching device of claim 9, wherein the first and second electrodes are on a same contiguous portion of the semiconductor layer.
The graphene switching device of claim 9, wherein a bottommost surface of the graphene layer, a bottommost surface of the first electrode, and a bottommost surface of the insulating layer are on an upper surface of the semiconductor layer.
A graphene switching device having a tunable barrier, comprising: a graphene layer including a first surface opposite a second surface; a semiconductor layer containing one of an n-type impurity and a p-type impurity, the semiconductor layer contacting one of a first part of the first surface of the graphene layer and a first part of the second surface of the graphene layer, the graphene layer having a zero band gap; a first electrode contacting the semiconductor layer, the first electrode being separated from the graphene layer, a second electrode contacting a second part of the first surface of the graphene layer; a gate electrode; and a gate dielectric contacting the gate electrode and the graphene layer, the gate dielectric being between the gate electrode and the semiconductor layer.
(Origin al) The graphene switching device of claim 17, wherein the semiconductor layer includes one of silicon, germanium, silicon-germanium, a group III -V semiconductor, and a group I I -VI semiconductor.
The graphene switching device of claim 17, wherein at least one of the first and second electrodes contains one of metal and polysi l icon.
The graphene switching device of claim 17, wherein at least a portion of the graphene layer has a thickness of one to four layers of graphene.
The graphene switching device of claim 17, wherein the graphene switching device is a uni-polar transistor having a polarity that is the same as an impurity type of the semiconductor layer.
The graphene switching device of claim 17, wherein the gate dielectric is on the gate electrode, the graphene layer is on the gate dielectric, the semiconductor layer is on the graphene layer and contacts the first part of the first surface of the graphene layer, the first electrode is on the semiconductor layer, and the second electrode is spaced apart from the semiconductor layer on the first surface of the graphene layer. withdrawn
The graphene switching device of claim 17, wherein the semiconductor layer contacts the first part of the second surface of the graphene layer, the graphene layer is on the semiconductor layer, the first electrode is on the semiconductor layer, the gate dielectric is on the graphene layer, and the gate electrode is on the gate dielectric.
The graphene switching device of claim 17, wherein the graphene layer is configured to function as a pathway for one of electrons and holes flowing through the graphene layer when a gate voltage is applied to the gate electrode.
The graphene switching device of claim 17, further comprising: an insulating layer below the second electrode and the graphene layer, wherein a bottommost surface of the graphene layer, a bottommost surface of the first electrode, and a bottommost surface of the insulating layer are on an upper surface of the semiconductor layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene switching device with tunable barrier (semiconductor-on-graphene topology)
graphene switching device with tunable barrier (graphene two-surface topology)
Materials described outside the worked examples.
graphene
C
semiconductor layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is an I-V characteristic curve of an n-type graphene switching device according to example embodiments; [0043]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness |
silicon
Si
germanium
Ge
silicon-germanium
SiGe
FIG. 4 is an I-V characteristic curve of a p-type graphene switching device according to example embodiments; [0044]
| — |
silicon
Si
germanium
Ge
silicon-germanium
SiGe
FIG. 4 is an I-V characteristic curve of a p-type graphene switching device according to example embodiments; [0044]
| — |
silicon
Si
germanium
Ge
silicon-germanium
SiGe
FIG. 4 is an I-V characteristic curve of a p-type graphene switching device according to example embodiments; [0044]
| — |
silicon
Si
germanium
Ge
silicon-germanium
SiGe
FIG. 4 is an I-V characteristic curve of a p-type graphene switching device according to example embodiments; [0044]
| — |