Patent
US 9,772,448GRAPHENE PLASMONIC COMMUNICATION LINK
PHAEDON AVOURIS
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,772,448Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a top view of a plasmonic link in accordance with the present principles; [0010]
FIG. 2 is a side cross-sectional view of the plasmonic link of
FIG. 3 is a top view of an integrated circuit having one or more plasmonic links between components of an integrated circuit in accordance with one embodiment; …
FIG. 4 is a top view of two integrated circuit chips having one or more plasmonic links between the chips in accordance with another embodiment; [0013]
FIG. 5 is a side view of two stacks of an integrated circuit chips showing plasmonic links between chips in a same vertical stack and between chips in different …
FIG. 6 is a block/flow diagram showing two integrated circuit chips having a plasmonic link and impedance transformation between a data source (transmitter) and …
FIG. 7 is a block/flow diagram showing a system for modulating a signal using a plasmonic channel/link and a gate field in accordance with another embodiment; …
FIG. 8 is a block/flow diagram showing a method for high frequency signal transfer in accordance with one illustrative embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A signal transfer link, comprising: a first plasmonic coupler; a second plasmonic coupler spaced apart from the first plasmonic coupler to form a gap; a plasmonic conductive layer formed over the gap to excite plasmons to provide signal transmission between the first and second plasmonic couplers; and at least one gate structure present over the plasmonic conductive layer that provides a gate field for modulating the signal transmission in the signal transfer link, wherein changing a gate area of the at least one gate structure causes a phase shift in the signal transmission.
The link as recited in claim 1, wherein the plasmonic conductive layer includes graphene.
The link as recited in claim 1, wherein the first and second plasmonic couplers include nanoantennae.
The link as recited in claim 1, wherein the link includes a communication link between at least two components on an integrated circuit chip.
The link as recited in claim 1, wherein the link includes a communication link between at least two integrated circuit chips. -2-
The link as recited in claim 1, further comprising at least one impedance transformation component to adjust impedance for signal transfer.
The link as recited in claim 1, wherein the link is flexible.
The link as recited in claim 1, wherein the link is visibly transparent.
The link as recited in claim 1, wherein the link provides data transfer at a rate of between 100 GHz and 10 THz.
The link as recited in claim 1, wherein the plasmonic conductive layer includes a metal grating.
A signal transfer link, comprising: a first plasmonic coupler; a second plasmonic coupler disposed in a same plane as the first plasmonic coupler and spaced apart from the first plasmonic coupler by a gap; a plasmonic conductive layer including graphene formed over the gap and overlapping the end portions of the first and second plasmonic couplers such that an electrical signal from one of the first and second plasmonic couplers is converted to a plasmonic signal in the plasmonic conductive layer; and at least one gate structure present over the plasmonic conductive layer that provides a gate field for modulating the plasmonic signal in the signal transfer link, wherein changing a -3- gate area of the at least one gate structure causes a phase shift in the plasmonic signal. 12. The link as recited in claim 11, wherein the plasmonic signal is then conve rt ed back to an electrical signal in the other of the first and second plasmonic couplers. 13. The link as recited in claim 11, wherein the link includes a communication link between at least two components on an integrated circuit chip. 14. The link as recited in claim 11, wherein the link includes a communication link between at least two integrated circuit chips. 15. The link as recited in claim 11, further comprising at least one impedance transformation component to adjust impedance for signal transfer. 16. The link as recited in claim 11, wherein the link is flexible and visibly transparent.
The link as recited in claim 11, wherein the link includes a gate field, wherein the gate field is selectively enabled to modulate a signal in the link. 18. The link as recited in claim 11, wherein the link provides data transfer at a rate of between 100 GHz and 10 THz. -4-
Layer stacks claimed or described, ordered top of device to substrate.
signal transfer link (generic plasmonic conductive layer)
signal transfer link (graphene plasmonic conductive layer)
Materials described outside the worked examples.
plasmonic conductive layer
graphene
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a side view of two stacks of an integrated circuit chips showing plasmonic links between chips in a same vertical stack and between chips in different …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–40 nm | — |
Thickness | 0.24–24 µm |
Patent
Atlas literature
Patent
US 9,772,448Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a top view of a plasmonic link in accordance with the present principles; [0010]
FIG. 2 is a side cross-sectional view of the plasmonic link of
FIG. 3 is a top view of an integrated circuit having one or more plasmonic links between components of an integrated circuit in accordance with one embodiment; …
FIG. 4 is a top view of two integrated circuit chips having one or more plasmonic links between the chips in accordance with another embodiment; [0013]
FIG. 5 is a side view of two stacks of an integrated circuit chips showing plasmonic links between chips in a same vertical stack and between chips in different …
FIG. 6 is a block/flow diagram showing two integrated circuit chips having a plasmonic link and impedance transformation between a data source (transmitter) and …
FIG. 7 is a block/flow diagram showing a system for modulating a signal using a plasmonic channel/link and a gate field in accordance with another embodiment; …
FIG. 8 is a block/flow diagram showing a method for high frequency signal transfer in accordance with one illustrative embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A signal transfer link, comprising: a first plasmonic coupler; a second plasmonic coupler spaced apart from the first plasmonic coupler to form a gap; a plasmonic conductive layer formed over the gap to excite plasmons to provide signal transmission between the first and second plasmonic couplers; and at least one gate structure present over the plasmonic conductive layer that provides a gate field for modulating the signal transmission in the signal transfer link, wherein changing a gate area of the at least one gate structure causes a phase shift in the signal transmission.
The link as recited in claim 1, wherein the plasmonic conductive layer includes graphene.
The link as recited in claim 1, wherein the first and second plasmonic couplers include nanoantennae.
The link as recited in claim 1, wherein the link includes a communication link between at least two components on an integrated circuit chip.
The link as recited in claim 1, wherein the link includes a communication link between at least two integrated circuit chips. -2-
The link as recited in claim 1, further comprising at least one impedance transformation component to adjust impedance for signal transfer.
The link as recited in claim 1, wherein the link is flexible.
The link as recited in claim 1, wherein the link is visibly transparent.
The link as recited in claim 1, wherein the link provides data transfer at a rate of between 100 GHz and 10 THz.
The link as recited in claim 1, wherein the plasmonic conductive layer includes a metal grating.
A signal transfer link, comprising: a first plasmonic coupler; a second plasmonic coupler disposed in a same plane as the first plasmonic coupler and spaced apart from the first plasmonic coupler by a gap; a plasmonic conductive layer including graphene formed over the gap and overlapping the end portions of the first and second plasmonic couplers such that an electrical signal from one of the first and second plasmonic couplers is converted to a plasmonic signal in the plasmonic conductive layer; and at least one gate structure present over the plasmonic conductive layer that provides a gate field for modulating the plasmonic signal in the signal transfer link, wherein changing a -3- gate area of the at least one gate structure causes a phase shift in the plasmonic signal. 12. The link as recited in claim 11, wherein the plasmonic signal is then conve rt ed back to an electrical signal in the other of the first and second plasmonic couplers. 13. The link as recited in claim 11, wherein the link includes a communication link between at least two components on an integrated circuit chip. 14. The link as recited in claim 11, wherein the link includes a communication link between at least two integrated circuit chips. 15. The link as recited in claim 11, further comprising at least one impedance transformation component to adjust impedance for signal transfer. 16. The link as recited in claim 11, wherein the link is flexible and visibly transparent.
The link as recited in claim 11, wherein the link includes a gate field, wherein the gate field is selectively enabled to modulate a signal in the link. 18. The link as recited in claim 11, wherein the link provides data transfer at a rate of between 100 GHz and 10 THz. -4-
Layer stacks claimed or described, ordered top of device to substrate.
signal transfer link (generic plasmonic conductive layer)
signal transfer link (graphene plasmonic conductive layer)
Materials described outside the worked examples.
plasmonic conductive layer
graphene
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a side view of two stacks of an integrated circuit chips showing plasmonic links between chips in a same vertical stack and between chips in different …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–40 nm | — |
Thickness | 0.24–24 µm |
Patent
Atlas literature
Patent
US 9,772,448Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a top view of a plasmonic link in accordance with the present principles; [0010]
FIG. 2 is a side cross-sectional view of the plasmonic link of
FIG. 3 is a top view of an integrated circuit having one or more plasmonic links between components of an integrated circuit in accordance with one embodiment; …
FIG. 4 is a top view of two integrated circuit chips having one or more plasmonic links between the chips in accordance with another embodiment; [0013]
FIG. 5 is a side view of two stacks of an integrated circuit chips showing plasmonic links between chips in a same vertical stack and between chips in different …
FIG. 6 is a block/flow diagram showing two integrated circuit chips having a plasmonic link and impedance transformation between a data source (transmitter) and …
FIG. 7 is a block/flow diagram showing a system for modulating a signal using a plasmonic channel/link and a gate field in accordance with another embodiment; …
FIG. 8 is a block/flow diagram showing a method for high frequency signal transfer in accordance with one illustrative embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A signal transfer link, comprising: a first plasmonic coupler; a second plasmonic coupler spaced apart from the first plasmonic coupler to form a gap; a plasmonic conductive layer formed over the gap to excite plasmons to provide signal transmission between the first and second plasmonic couplers; and at least one gate structure present over the plasmonic conductive layer that provides a gate field for modulating the signal transmission in the signal transfer link, wherein changing a gate area of the at least one gate structure causes a phase shift in the signal transmission.
The link as recited in claim 1, wherein the plasmonic conductive layer includes graphene.
The link as recited in claim 1, wherein the first and second plasmonic couplers include nanoantennae.
The link as recited in claim 1, wherein the link includes a communication link between at least two components on an integrated circuit chip.
The link as recited in claim 1, wherein the link includes a communication link between at least two integrated circuit chips. -2-
The link as recited in claim 1, further comprising at least one impedance transformation component to adjust impedance for signal transfer.
The link as recited in claim 1, wherein the link is flexible.
The link as recited in claim 1, wherein the link is visibly transparent.
The link as recited in claim 1, wherein the link provides data transfer at a rate of between 100 GHz and 10 THz.
The link as recited in claim 1, wherein the plasmonic conductive layer includes a metal grating.
A signal transfer link, comprising: a first plasmonic coupler; a second plasmonic coupler disposed in a same plane as the first plasmonic coupler and spaced apart from the first plasmonic coupler by a gap; a plasmonic conductive layer including graphene formed over the gap and overlapping the end portions of the first and second plasmonic couplers such that an electrical signal from one of the first and second plasmonic couplers is converted to a plasmonic signal in the plasmonic conductive layer; and at least one gate structure present over the plasmonic conductive layer that provides a gate field for modulating the plasmonic signal in the signal transfer link, wherein changing a -3- gate area of the at least one gate structure causes a phase shift in the plasmonic signal. 12. The link as recited in claim 11, wherein the plasmonic signal is then conve rt ed back to an electrical signal in the other of the first and second plasmonic couplers. 13. The link as recited in claim 11, wherein the link includes a communication link between at least two components on an integrated circuit chip. 14. The link as recited in claim 11, wherein the link includes a communication link between at least two integrated circuit chips. 15. The link as recited in claim 11, further comprising at least one impedance transformation component to adjust impedance for signal transfer. 16. The link as recited in claim 11, wherein the link is flexible and visibly transparent.
The link as recited in claim 11, wherein the link includes a gate field, wherein the gate field is selectively enabled to modulate a signal in the link. 18. The link as recited in claim 11, wherein the link provides data transfer at a rate of between 100 GHz and 10 THz. -4-
Layer stacks claimed or described, ordered top of device to substrate.
signal transfer link (generic plasmonic conductive layer)
signal transfer link (graphene plasmonic conductive layer)
Materials described outside the worked examples.
plasmonic conductive layer
graphene
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a side view of two stacks of an integrated circuit chips showing plasmonic links between chips in a same vertical stack and between chips in different …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–40 nm | — |
Thickness | 0.24–24 µm |
Patent
Atlas literature
Patent
US 9,772,448Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a top view of a plasmonic link in accordance with the present principles; [0010]
FIG. 2 is a side cross-sectional view of the plasmonic link of
FIG. 3 is a top view of an integrated circuit having one or more plasmonic links between components of an integrated circuit in accordance with one embodiment; …
FIG. 4 is a top view of two integrated circuit chips having one or more plasmonic links between the chips in accordance with another embodiment; [0013]
FIG. 5 is a side view of two stacks of an integrated circuit chips showing plasmonic links between chips in a same vertical stack and between chips in different …
FIG. 6 is a block/flow diagram showing two integrated circuit chips having a plasmonic link and impedance transformation between a data source (transmitter) and …
FIG. 7 is a block/flow diagram showing a system for modulating a signal using a plasmonic channel/link and a gate field in accordance with another embodiment; …
FIG. 8 is a block/flow diagram showing a method for high frequency signal transfer in accordance with one illustrative embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A signal transfer link, comprising: a first plasmonic coupler; a second plasmonic coupler spaced apart from the first plasmonic coupler to form a gap; a plasmonic conductive layer formed over the gap to excite plasmons to provide signal transmission between the first and second plasmonic couplers; and at least one gate structure present over the plasmonic conductive layer that provides a gate field for modulating the signal transmission in the signal transfer link, wherein changing a gate area of the at least one gate structure causes a phase shift in the signal transmission.
The link as recited in claim 1, wherein the plasmonic conductive layer includes graphene.
The link as recited in claim 1, wherein the first and second plasmonic couplers include nanoantennae.
The link as recited in claim 1, wherein the link includes a communication link between at least two components on an integrated circuit chip.
The link as recited in claim 1, wherein the link includes a communication link between at least two integrated circuit chips. -2-
The link as recited in claim 1, further comprising at least one impedance transformation component to adjust impedance for signal transfer.
The link as recited in claim 1, wherein the link is flexible.
The link as recited in claim 1, wherein the link is visibly transparent.
The link as recited in claim 1, wherein the link provides data transfer at a rate of between 100 GHz and 10 THz.
The link as recited in claim 1, wherein the plasmonic conductive layer includes a metal grating.
A signal transfer link, comprising: a first plasmonic coupler; a second plasmonic coupler disposed in a same plane as the first plasmonic coupler and spaced apart from the first plasmonic coupler by a gap; a plasmonic conductive layer including graphene formed over the gap and overlapping the end portions of the first and second plasmonic couplers such that an electrical signal from one of the first and second plasmonic couplers is converted to a plasmonic signal in the plasmonic conductive layer; and at least one gate structure present over the plasmonic conductive layer that provides a gate field for modulating the plasmonic signal in the signal transfer link, wherein changing a -3- gate area of the at least one gate structure causes a phase shift in the plasmonic signal. 12. The link as recited in claim 11, wherein the plasmonic signal is then conve rt ed back to an electrical signal in the other of the first and second plasmonic couplers. 13. The link as recited in claim 11, wherein the link includes a communication link between at least two components on an integrated circuit chip. 14. The link as recited in claim 11, wherein the link includes a communication link between at least two integrated circuit chips. 15. The link as recited in claim 11, further comprising at least one impedance transformation component to adjust impedance for signal transfer. 16. The link as recited in claim 11, wherein the link is flexible and visibly transparent.
The link as recited in claim 11, wherein the link includes a gate field, wherein the gate field is selectively enabled to modulate a signal in the link. 18. The link as recited in claim 11, wherein the link provides data transfer at a rate of between 100 GHz and 10 THz. -4-
Layer stacks claimed or described, ordered top of device to substrate.
signal transfer link (generic plasmonic conductive layer)
signal transfer link (graphene plasmonic conductive layer)
Materials described outside the worked examples.
plasmonic conductive layer
graphene
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a side view of two stacks of an integrated circuit chips showing plasmonic links between chips in a same vertical stack and between chips in different …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–40 nm | — |
Thickness | 0.24–24 µm |
plasmon-based communication link (description embodiment)
metal grating
insulator
thermal oxide/high-k dielectric/PMMA
| — |
Thickness | 2.4–240 µm | — |
Thickness | 6.6–20.7 µm | — |
Thickness | 660000–2000000 nm | — |
Voltage | 0–2 V | — |
Thickness | ≤ 50 nm | — |
plasmon-based communication link (description embodiment)
metal grating
insulator
thermal oxide/high-k dielectric/PMMA
| — |
Thickness | 2.4–240 µm | — |
Thickness | 6.6–20.7 µm | — |
Thickness | 660000–2000000 nm | — |
Voltage | 0–2 V | — |
Thickness | ≤ 50 nm | — |
plasmon-based communication link (description embodiment)
metal grating
insulator
thermal oxide/high-k dielectric/PMMA
| — |
Thickness | 2.4–240 µm | — |
Thickness | 6.6–20.7 µm | — |
Thickness | 660000–2000000 nm | — |
Voltage | 0–2 V | — |
Thickness | ≤ 50 nm | — |
plasmon-based communication link (description embodiment)
metal grating
insulator
thermal oxide/high-k dielectric/PMMA
| — |
Thickness | 2.4–240 µm | — |
Thickness | 6.6–20.7 µm | — |
Thickness | 660000–2000000 nm | — |
Voltage | 0–2 V | — |
Thickness | ≤ 50 nm | — |