Patent
US 9,431,520GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SiC FINS OR NANOWIRE TEMPLATES
Guy M. Cohen
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,431,520Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) depicting a silicon carbide-on-insulator substrate that can be employed in one embodiment …
FIGS. 2A-2D are pictorial representation (through cross sectional views) depicting one possible method that can be used in forming the silicon …
FIG. 3 after forming a plurality of silicon carbide fins that include a patterned hard mask thereon in at least one region of the substrate. [0022]
FIG. 4A after forming graphene nanoribbons on bare sidewalls of each of the silicon carbide fins. [0024]
FIG. 5A after forming a gate structure including a gate dielectric and a gate conductor on a portion of each silicon carbide fin which includes graphene …
FIG. 6B is a pictorial side-view representation through cut B₁-B₂ shown in the top down view of
FIGS. 7A-7 B are pictorial representations illustrating that the type of graphene that can be formed on the sidewalls of the silicon carbide fins provided in
FIG. 8 is a pictorial representation (through a cross sectional view) illustrating a silicon- on-insulator substrate including, from bottom to top, a handle …
FIG. 9 is a pictorial representation (through a cross sectional view) illustrating the silicon- on-insulator substrate of
FIG. 10 after forming silicon carbide fins on the bare sidewalls of the silicon fin. [0032]
FIG. 11 after forming a graphene nanoribbon on bare sidewalls of each silicon carbide fin. [0033]
FIG. 12 after forming a first gate structure including a first gate dielectric and a first gate conductor thereon. [0034]
FIG. 13 is a three dimensional representation of the structure shown in
FIG. 14 after forming a planarizing dielectric layer and planarizing the structure stopping on an upper surface of the patterned hard mask. [0036]
FIG. 15 is a pictorial representation (through a cross sectional view) illustrating the structure shown in
FIG. 16 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 17 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIGS. 18A-18B are pictorial representations (through cross sectional views) illustrating the structure of
FIG. 19A after forming a graphene coating on all exposed surfaces of the plurality of suspended silicon carbide nanowires; the nanowires coated with graphene …
FIG. 20A after forming a gate structure including a gate dielectric and a gate conductor over a portion of each carbon nanotube. [0044]
FIG. 21A is a pictorial representation (through a top down view) of the structure shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method of forming a semiconductor structure comprising: providing at least one silicon fin on a surface of a substrate; forming a silicon carbide fin on each bare sidewall of said at least one silicon fin; forming a graphene nanoribbon on a sidewall of each silicon carbide fin; and forming a gate structure oriented perpendicular to each silicon carbide fin and said at least one silicon fin, said gate structure overlapping a portion of each graphene nanoribbon and located atop a portion of each of said silicon carbide fins and said at least one silicon fin, wherein said portion of each graphene nanoribbon overlapped by said gate structure defines a channel region of said semiconductor structure.
The method of Claim 17, wherein said providing said at least one silicon fin comp ri ses: providing a silicon-on-insulator substrate comprising, from bottom to top, a handle substrate, an insulator layer and a silicon layer; forming a hard mask on a surface of said silicon layer; patterning said hard mask and said silicon layer by lithography and etching to provide said at least one silicon fin.
The method of Claim 17, wherein said forming said silicon carbide fin comprises a selective epitaxial growth process.
The method of Claim 17, wherein said silicon carbide fins have a same height as said at least one silicon fin.
The method of Claim 17, wherein said forming said graphene nanoribbon comp ri ses: 3 I: \GF- I BM\2683\27054ZA\AMEND\27054ZA.PA.doc cleaning each sidewall of said silicon carbide fins, said cleaning comprising a first anneal in a silane-containing ambient; and performing a second anneal to grow said graphene nanoribbons, wherein said second anneal is performed at a temperature lower than a melting temperature of silicon.
The method of Claim 17, wherein each graphene nanoribbon has a height that is equal to a height of said silicon carbide fins.
The method of Claim 17, wherein a topmost surface of said at least one silicon fin is coplanar with a topmost surface of each silicon carbide fin and a topmost surface of each graphene nanoribbon.
A method of forming a semiconductor structure comprising: providing at least one pair of spaced apart graphene nanoribbons on a surface of a substrate; forming a first gate structure on one sidewall of each spaced apart graphene nanoribbon, said sidewalls of each graphene nanoribbon containing said first gate structure are not facing each other; 2 I:\GF- I BM\2683\27054ZA\AMEND\27054ZA.PA.doc forming a planarizing dielectric material adjacent said first gate structure; and forming at least a gate conductor of a second gate structure located between said at least one pair of spaced apart graphene nanoribbons.
The method of Claim 18, wherein said providing said at least one pair of spaced apart graphene nanoribbons comprises: providing a silicon fin on a surface of said substrate; forming a silicon carbide fin on each bare sidewall of said silicon fin; forming a graphene nanoribbon on a sidewall of each silicon carbide fin; and 4 I:\GF- I BM\2683\27054ZA\AMEND\27054ZA.PA.doc removing said silicon fin and each silicon carbide fin.
Layer stacks claimed or described, ordered top of device to substrate.
dual-channel finFET with graphene nanoribbon channel
dual-gate graphene nanoribbon FET
Materials described outside the worked examples.
graphene nanoribbon
silicon carbide fin
SiC
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–10 nm | — |
Thickness |
Patent
Atlas literature
Patent
US 9,431,520Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) depicting a silicon carbide-on-insulator substrate that can be employed in one embodiment …
FIGS. 2A-2D are pictorial representation (through cross sectional views) depicting one possible method that can be used in forming the silicon …
FIG. 3 after forming a plurality of silicon carbide fins that include a patterned hard mask thereon in at least one region of the substrate. [0022]
FIG. 4A after forming graphene nanoribbons on bare sidewalls of each of the silicon carbide fins. [0024]
FIG. 5A after forming a gate structure including a gate dielectric and a gate conductor on a portion of each silicon carbide fin which includes graphene …
FIG. 6B is a pictorial side-view representation through cut B₁-B₂ shown in the top down view of
FIGS. 7A-7 B are pictorial representations illustrating that the type of graphene that can be formed on the sidewalls of the silicon carbide fins provided in
FIG. 8 is a pictorial representation (through a cross sectional view) illustrating a silicon- on-insulator substrate including, from bottom to top, a handle …
FIG. 9 is a pictorial representation (through a cross sectional view) illustrating the silicon- on-insulator substrate of
FIG. 10 after forming silicon carbide fins on the bare sidewalls of the silicon fin. [0032]
FIG. 11 after forming a graphene nanoribbon on bare sidewalls of each silicon carbide fin. [0033]
FIG. 12 after forming a first gate structure including a first gate dielectric and a first gate conductor thereon. [0034]
FIG. 13 is a three dimensional representation of the structure shown in
FIG. 14 after forming a planarizing dielectric layer and planarizing the structure stopping on an upper surface of the patterned hard mask. [0036]
FIG. 15 is a pictorial representation (through a cross sectional view) illustrating the structure shown in
FIG. 16 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 17 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIGS. 18A-18B are pictorial representations (through cross sectional views) illustrating the structure of
FIG. 19A after forming a graphene coating on all exposed surfaces of the plurality of suspended silicon carbide nanowires; the nanowires coated with graphene …
FIG. 20A after forming a gate structure including a gate dielectric and a gate conductor over a portion of each carbon nanotube. [0044]
FIG. 21A is a pictorial representation (through a top down view) of the structure shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method of forming a semiconductor structure comprising: providing at least one silicon fin on a surface of a substrate; forming a silicon carbide fin on each bare sidewall of said at least one silicon fin; forming a graphene nanoribbon on a sidewall of each silicon carbide fin; and forming a gate structure oriented perpendicular to each silicon carbide fin and said at least one silicon fin, said gate structure overlapping a portion of each graphene nanoribbon and located atop a portion of each of said silicon carbide fins and said at least one silicon fin, wherein said portion of each graphene nanoribbon overlapped by said gate structure defines a channel region of said semiconductor structure.
The method of Claim 17, wherein said providing said at least one silicon fin comp ri ses: providing a silicon-on-insulator substrate comprising, from bottom to top, a handle substrate, an insulator layer and a silicon layer; forming a hard mask on a surface of said silicon layer; patterning said hard mask and said silicon layer by lithography and etching to provide said at least one silicon fin.
The method of Claim 17, wherein said forming said silicon carbide fin comprises a selective epitaxial growth process.
The method of Claim 17, wherein said silicon carbide fins have a same height as said at least one silicon fin.
The method of Claim 17, wherein said forming said graphene nanoribbon comp ri ses: 3 I: \GF- I BM\2683\27054ZA\AMEND\27054ZA.PA.doc cleaning each sidewall of said silicon carbide fins, said cleaning comprising a first anneal in a silane-containing ambient; and performing a second anneal to grow said graphene nanoribbons, wherein said second anneal is performed at a temperature lower than a melting temperature of silicon.
The method of Claim 17, wherein each graphene nanoribbon has a height that is equal to a height of said silicon carbide fins.
The method of Claim 17, wherein a topmost surface of said at least one silicon fin is coplanar with a topmost surface of each silicon carbide fin and a topmost surface of each graphene nanoribbon.
A method of forming a semiconductor structure comprising: providing at least one pair of spaced apart graphene nanoribbons on a surface of a substrate; forming a first gate structure on one sidewall of each spaced apart graphene nanoribbon, said sidewalls of each graphene nanoribbon containing said first gate structure are not facing each other; 2 I:\GF- I BM\2683\27054ZA\AMEND\27054ZA.PA.doc forming a planarizing dielectric material adjacent said first gate structure; and forming at least a gate conductor of a second gate structure located between said at least one pair of spaced apart graphene nanoribbons.
The method of Claim 18, wherein said providing said at least one pair of spaced apart graphene nanoribbons comprises: providing a silicon fin on a surface of said substrate; forming a silicon carbide fin on each bare sidewall of said silicon fin; forming a graphene nanoribbon on a sidewall of each silicon carbide fin; and 4 I:\GF- I BM\2683\27054ZA\AMEND\27054ZA.PA.doc removing said silicon fin and each silicon carbide fin.
Layer stacks claimed or described, ordered top of device to substrate.
dual-channel finFET with graphene nanoribbon channel
dual-gate graphene nanoribbon FET
Materials described outside the worked examples.
graphene nanoribbon
silicon carbide fin
SiC
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–10 nm | — |
Thickness |
Patent
Atlas literature
Patent
US 9,431,520Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) depicting a silicon carbide-on-insulator substrate that can be employed in one embodiment …
FIGS. 2A-2D are pictorial representation (through cross sectional views) depicting one possible method that can be used in forming the silicon …
FIG. 3 after forming a plurality of silicon carbide fins that include a patterned hard mask thereon in at least one region of the substrate. [0022]
FIG. 4A after forming graphene nanoribbons on bare sidewalls of each of the silicon carbide fins. [0024]
FIG. 5A after forming a gate structure including a gate dielectric and a gate conductor on a portion of each silicon carbide fin which includes graphene …
FIG. 6B is a pictorial side-view representation through cut B₁-B₂ shown in the top down view of
FIGS. 7A-7 B are pictorial representations illustrating that the type of graphene that can be formed on the sidewalls of the silicon carbide fins provided in
FIG. 8 is a pictorial representation (through a cross sectional view) illustrating a silicon- on-insulator substrate including, from bottom to top, a handle …
FIG. 9 is a pictorial representation (through a cross sectional view) illustrating the silicon- on-insulator substrate of
FIG. 10 after forming silicon carbide fins on the bare sidewalls of the silicon fin. [0032]
FIG. 11 after forming a graphene nanoribbon on bare sidewalls of each silicon carbide fin. [0033]
FIG. 12 after forming a first gate structure including a first gate dielectric and a first gate conductor thereon. [0034]
FIG. 13 is a three dimensional representation of the structure shown in
FIG. 14 after forming a planarizing dielectric layer and planarizing the structure stopping on an upper surface of the patterned hard mask. [0036]
FIG. 15 is a pictorial representation (through a cross sectional view) illustrating the structure shown in
FIG. 16 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 17 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIGS. 18A-18B are pictorial representations (through cross sectional views) illustrating the structure of
FIG. 19A after forming a graphene coating on all exposed surfaces of the plurality of suspended silicon carbide nanowires; the nanowires coated with graphene …
FIG. 20A after forming a gate structure including a gate dielectric and a gate conductor over a portion of each carbon nanotube. [0044]
FIG. 21A is a pictorial representation (through a top down view) of the structure shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method of forming a semiconductor structure comprising: providing at least one silicon fin on a surface of a substrate; forming a silicon carbide fin on each bare sidewall of said at least one silicon fin; forming a graphene nanoribbon on a sidewall of each silicon carbide fin; and forming a gate structure oriented perpendicular to each silicon carbide fin and said at least one silicon fin, said gate structure overlapping a portion of each graphene nanoribbon and located atop a portion of each of said silicon carbide fins and said at least one silicon fin, wherein said portion of each graphene nanoribbon overlapped by said gate structure defines a channel region of said semiconductor structure.
The method of Claim 17, wherein said providing said at least one silicon fin comp ri ses: providing a silicon-on-insulator substrate comprising, from bottom to top, a handle substrate, an insulator layer and a silicon layer; forming a hard mask on a surface of said silicon layer; patterning said hard mask and said silicon layer by lithography and etching to provide said at least one silicon fin.
The method of Claim 17, wherein said forming said silicon carbide fin comprises a selective epitaxial growth process.
The method of Claim 17, wherein said silicon carbide fins have a same height as said at least one silicon fin.
The method of Claim 17, wherein said forming said graphene nanoribbon comp ri ses: 3 I: \GF- I BM\2683\27054ZA\AMEND\27054ZA.PA.doc cleaning each sidewall of said silicon carbide fins, said cleaning comprising a first anneal in a silane-containing ambient; and performing a second anneal to grow said graphene nanoribbons, wherein said second anneal is performed at a temperature lower than a melting temperature of silicon.
The method of Claim 17, wherein each graphene nanoribbon has a height that is equal to a height of said silicon carbide fins.
The method of Claim 17, wherein a topmost surface of said at least one silicon fin is coplanar with a topmost surface of each silicon carbide fin and a topmost surface of each graphene nanoribbon.
A method of forming a semiconductor structure comprising: providing at least one pair of spaced apart graphene nanoribbons on a surface of a substrate; forming a first gate structure on one sidewall of each spaced apart graphene nanoribbon, said sidewalls of each graphene nanoribbon containing said first gate structure are not facing each other; 2 I:\GF- I BM\2683\27054ZA\AMEND\27054ZA.PA.doc forming a planarizing dielectric material adjacent said first gate structure; and forming at least a gate conductor of a second gate structure located between said at least one pair of spaced apart graphene nanoribbons.
The method of Claim 18, wherein said providing said at least one pair of spaced apart graphene nanoribbons comprises: providing a silicon fin on a surface of said substrate; forming a silicon carbide fin on each bare sidewall of said silicon fin; forming a graphene nanoribbon on a sidewall of each silicon carbide fin; and 4 I:\GF- I BM\2683\27054ZA\AMEND\27054ZA.PA.doc removing said silicon fin and each silicon carbide fin.
Layer stacks claimed or described, ordered top of device to substrate.
dual-channel finFET with graphene nanoribbon channel
dual-gate graphene nanoribbon FET
Materials described outside the worked examples.
graphene nanoribbon
silicon carbide fin
SiC
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–10 nm | — |
Thickness |
Patent
Atlas literature
Patent
US 9,431,520Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) depicting a silicon carbide-on-insulator substrate that can be employed in one embodiment …
FIGS. 2A-2D are pictorial representation (through cross sectional views) depicting one possible method that can be used in forming the silicon …
FIG. 3 after forming a plurality of silicon carbide fins that include a patterned hard mask thereon in at least one region of the substrate. [0022]
FIG. 4A after forming graphene nanoribbons on bare sidewalls of each of the silicon carbide fins. [0024]
FIG. 5A after forming a gate structure including a gate dielectric and a gate conductor on a portion of each silicon carbide fin which includes graphene …
FIG. 6B is a pictorial side-view representation through cut B₁-B₂ shown in the top down view of
FIGS. 7A-7 B are pictorial representations illustrating that the type of graphene that can be formed on the sidewalls of the silicon carbide fins provided in
FIG. 8 is a pictorial representation (through a cross sectional view) illustrating a silicon- on-insulator substrate including, from bottom to top, a handle …
FIG. 9 is a pictorial representation (through a cross sectional view) illustrating the silicon- on-insulator substrate of
FIG. 10 after forming silicon carbide fins on the bare sidewalls of the silicon fin. [0032]
FIG. 11 after forming a graphene nanoribbon on bare sidewalls of each silicon carbide fin. [0033]
FIG. 12 after forming a first gate structure including a first gate dielectric and a first gate conductor thereon. [0034]
FIG. 13 is a three dimensional representation of the structure shown in
FIG. 14 after forming a planarizing dielectric layer and planarizing the structure stopping on an upper surface of the patterned hard mask. [0036]
FIG. 15 is a pictorial representation (through a cross sectional view) illustrating the structure shown in
FIG. 16 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 17 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIGS. 18A-18B are pictorial representations (through cross sectional views) illustrating the structure of
FIG. 19A after forming a graphene coating on all exposed surfaces of the plurality of suspended silicon carbide nanowires; the nanowires coated with graphene …
FIG. 20A after forming a gate structure including a gate dielectric and a gate conductor over a portion of each carbon nanotube. [0044]
FIG. 21A is a pictorial representation (through a top down view) of the structure shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method of forming a semiconductor structure comprising: providing at least one silicon fin on a surface of a substrate; forming a silicon carbide fin on each bare sidewall of said at least one silicon fin; forming a graphene nanoribbon on a sidewall of each silicon carbide fin; and forming a gate structure oriented perpendicular to each silicon carbide fin and said at least one silicon fin, said gate structure overlapping a portion of each graphene nanoribbon and located atop a portion of each of said silicon carbide fins and said at least one silicon fin, wherein said portion of each graphene nanoribbon overlapped by said gate structure defines a channel region of said semiconductor structure.
The method of Claim 17, wherein said providing said at least one silicon fin comp ri ses: providing a silicon-on-insulator substrate comprising, from bottom to top, a handle substrate, an insulator layer and a silicon layer; forming a hard mask on a surface of said silicon layer; patterning said hard mask and said silicon layer by lithography and etching to provide said at least one silicon fin.
The method of Claim 17, wherein said forming said silicon carbide fin comprises a selective epitaxial growth process.
The method of Claim 17, wherein said silicon carbide fins have a same height as said at least one silicon fin.
The method of Claim 17, wherein said forming said graphene nanoribbon comp ri ses: 3 I: \GF- I BM\2683\27054ZA\AMEND\27054ZA.PA.doc cleaning each sidewall of said silicon carbide fins, said cleaning comprising a first anneal in a silane-containing ambient; and performing a second anneal to grow said graphene nanoribbons, wherein said second anneal is performed at a temperature lower than a melting temperature of silicon.
The method of Claim 17, wherein each graphene nanoribbon has a height that is equal to a height of said silicon carbide fins.
The method of Claim 17, wherein a topmost surface of said at least one silicon fin is coplanar with a topmost surface of each silicon carbide fin and a topmost surface of each graphene nanoribbon.
A method of forming a semiconductor structure comprising: providing at least one pair of spaced apart graphene nanoribbons on a surface of a substrate; forming a first gate structure on one sidewall of each spaced apart graphene nanoribbon, said sidewalls of each graphene nanoribbon containing said first gate structure are not facing each other; 2 I:\GF- I BM\2683\27054ZA\AMEND\27054ZA.PA.doc forming a planarizing dielectric material adjacent said first gate structure; and forming at least a gate conductor of a second gate structure located between said at least one pair of spaced apart graphene nanoribbons.
The method of Claim 18, wherein said providing said at least one pair of spaced apart graphene nanoribbons comprises: providing a silicon fin on a surface of said substrate; forming a silicon carbide fin on each bare sidewall of said silicon fin; forming a graphene nanoribbon on a sidewall of each silicon carbide fin; and 4 I:\GF- I BM\2683\27054ZA\AMEND\27054ZA.PA.doc removing said silicon fin and each silicon carbide fin.
Layer stacks claimed or described, ordered top of device to substrate.
dual-channel finFET with graphene nanoribbon channel
dual-gate graphene nanoribbon FET
Materials described outside the worked examples.
graphene nanoribbon
silicon carbide fin
SiC
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–10 nm | — |
Thickness |
silicon fin
Si
planarizing dielectric material
silicon-on-insulator substrate
carbon nanotube
| — |
Thickness | 1–200 nm | — |
Thickness | 100–150 nm | — |
Temperature | 300–1200 °C | — |
Duration | 0.5–24 hours | — |
Thickness | 0.1–0.3 nm | — |
Thickness | 5–50 nm | — |
Thickness | 10–20 nm | — |
Temperature | 1300–2000 °C | — |
Thickness | 1–20 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1–100 nm | — |
Thickness | 3–30 nm | — |
Thickness | 1–10 nm | — |
Thickness | 5–200 nm | — |
Thickness | 20–100 nm | — |
silicon fin
Si
planarizing dielectric material
silicon-on-insulator substrate
carbon nanotube
| — |
Thickness | 1–200 nm | — |
Thickness | 100–150 nm | — |
Temperature | 300–1200 °C | — |
Duration | 0.5–24 hours | — |
Thickness | 0.1–0.3 nm | — |
Thickness | 5–50 nm | — |
Thickness | 10–20 nm | — |
Temperature | 1300–2000 °C | — |
Thickness | 1–20 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1–100 nm | — |
Thickness | 3–30 nm | — |
Thickness | 1–10 nm | — |
Thickness | 5–200 nm | — |
Thickness | 20–100 nm | — |
silicon fin
Si
planarizing dielectric material
silicon-on-insulator substrate
carbon nanotube
| — |
Thickness | 1–200 nm | — |
Thickness | 100–150 nm | — |
Temperature | 300–1200 °C | — |
Duration | 0.5–24 hours | — |
Thickness | 0.1–0.3 nm | — |
Thickness | 5–50 nm | — |
Thickness | 10–20 nm | — |
Temperature | 1300–2000 °C | — |
Thickness | 1–20 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1–100 nm | — |
Thickness | 3–30 nm | — |
Thickness | 1–10 nm | — |
Thickness | 5–200 nm | — |
Thickness | 20–100 nm | — |
silicon fin
Si
planarizing dielectric material
silicon-on-insulator substrate
carbon nanotube
| — |
Thickness | 1–200 nm | — |
Thickness | 100–150 nm | — |
Temperature | 300–1200 °C | — |
Duration | 0.5–24 hours | — |
Thickness | 0.1–0.3 nm | — |
Thickness | 5–50 nm | — |
Thickness | 10–20 nm | — |
Temperature | 1300–2000 °C | — |
Thickness | 1–20 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1–100 nm | — |
Thickness | 3–30 nm | — |
Thickness | 1–10 nm | — |
Thickness | 5–200 nm | — |
Thickness | 20–100 nm | — |