Patent
US 9,197,215GRAPHENE-BASED NON-BOOLEAN LOGIC CIRCUITS
Alexander A. Balandin
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,197,215Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A dual-gate transistor having a negative differential resistance (NDR) region comprising: " a back-gate; " a zero-bandgap graphene layer disposed on the back-gate; " a top-gate disposed on a portion of the zero-bandgap graphene layer; " a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate; and " a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate and displaced from the source, wherein the zero-bandgap graphene layer operates in the NDR region when a source-drain voltage and a top-gate voltage are simultaneously swept across a Dirac point.
The dual-gate transistor of claim 1 wherein the zero-bandgap graphene layer is made up of pristine graphene.
The dual-gate transistor of claim 1 wherein NDR is generated in a drift- diffusion regime at a micrometer scale.
The dual-gate transistor of claim 1 wherein NDR is generated in a ballistic regime at a nanometer scale.
The dual-gate transistor of claim 1 wherein the drain and source are diode- connected.
The dual-gate transistor of claim 1 wherein the zero-bandgap graphene layer comprises single layer graphene.
The dual-gate transistor of claim 1 wherein the zero-bandgap graphene layer comprises bilayer graphene.
Cancelled.
The dual-gate transistor of claim [[2]] 1 wherein a sweeping range for the top-gate voltage and the source-drain voltage is defined by a top-gate capacitance in a position of the Dirac point.
A graphene-based pattern matching circuit comprising: " a plurality of elementary cells coupled in series, each elementary cell comprising: " a first G-FET having a first back-gate that is a first input; " a second G-FET having a second back-gate that is a second input; and " a third G-FET having a current output coupled in series with an adjacent one of the plurality of elementary cells and a third back-gate that is coupled to top-gates of the first G-FET and the second G-FET.
The graphene-based pattern matching circuit of claim 11 wherein current flowing through the third G-FET decreases with a decrease of a Hamming distance between an input data string coupled to the first input and a reference data string coupled to the second input.
The graphene-based pattern matching circuit of claim 11 having an operational frequency range of from around about 100 GHz to around about 500 GHz.
The graphene-based pattern matching circuit of claim 11 having a maximum pattern matching throughput of around about 1022 bits/s/cm2.
The graphene-based pattern matching circuit of claim 11 wherein each of the plurality of elementary cells provides an exclusive OR (XOR) function.
The graphene-based pattern matching circuit of claim 11 wherein each G- FET is a dual-gate transistor having an NDR region comprising: " a back-gate; " a zero-bandgap graphene layer disposed on the back-gate; " a top-gate disposed on a portion of the zero-bandgap graphene layer; " a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate; and " a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate and displaced from the source.
An apparatus comprising: a dual-gate transistor having a negative differential resistance (NDR) region comprising: " a back-gate; " a zero-bandgap graphene layer disposed on the back-gate; " a top-gate disposed on a portion of the zero-bandgap graphene layer; 4 Serial No. 14/268,765 Attorney Docket No. 1186-020/P₁₄₆₀ " a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate; and " a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate and displaced from the source; and a dynamic bias controller adapted to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to cause the dual-gate transistor to operate within the NDR region.
Layer stacks claimed or described, ordered top of device to substrate.
dual-gate graphene transistor with NDR region (G-FET)
graphene-based pattern matching circuit
No layer stack recorded.
apparatus with dual-gate transistor and dynamic bias controller
Materials described outside the worked examples.
zero-bandgap graphene
C
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 50–70 V | — |
Voltage | 1–2 V |
Patent
Atlas literature
Patent
US 9,197,215Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A dual-gate transistor having a negative differential resistance (NDR) region comprising: " a back-gate; " a zero-bandgap graphene layer disposed on the back-gate; " a top-gate disposed on a portion of the zero-bandgap graphene layer; " a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate; and " a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate and displaced from the source, wherein the zero-bandgap graphene layer operates in the NDR region when a source-drain voltage and a top-gate voltage are simultaneously swept across a Dirac point.
The dual-gate transistor of claim 1 wherein the zero-bandgap graphene layer is made up of pristine graphene.
The dual-gate transistor of claim 1 wherein NDR is generated in a drift- diffusion regime at a micrometer scale.
The dual-gate transistor of claim 1 wherein NDR is generated in a ballistic regime at a nanometer scale.
The dual-gate transistor of claim 1 wherein the drain and source are diode- connected.
The dual-gate transistor of claim 1 wherein the zero-bandgap graphene layer comprises single layer graphene.
The dual-gate transistor of claim 1 wherein the zero-bandgap graphene layer comprises bilayer graphene.
Cancelled.
The dual-gate transistor of claim [[2]] 1 wherein a sweeping range for the top-gate voltage and the source-drain voltage is defined by a top-gate capacitance in a position of the Dirac point.
A graphene-based pattern matching circuit comprising: " a plurality of elementary cells coupled in series, each elementary cell comprising: " a first G-FET having a first back-gate that is a first input; " a second G-FET having a second back-gate that is a second input; and " a third G-FET having a current output coupled in series with an adjacent one of the plurality of elementary cells and a third back-gate that is coupled to top-gates of the first G-FET and the second G-FET.
The graphene-based pattern matching circuit of claim 11 wherein current flowing through the third G-FET decreases with a decrease of a Hamming distance between an input data string coupled to the first input and a reference data string coupled to the second input.
The graphene-based pattern matching circuit of claim 11 having an operational frequency range of from around about 100 GHz to around about 500 GHz.
The graphene-based pattern matching circuit of claim 11 having a maximum pattern matching throughput of around about 1022 bits/s/cm2.
The graphene-based pattern matching circuit of claim 11 wherein each of the plurality of elementary cells provides an exclusive OR (XOR) function.
The graphene-based pattern matching circuit of claim 11 wherein each G- FET is a dual-gate transistor having an NDR region comprising: " a back-gate; " a zero-bandgap graphene layer disposed on the back-gate; " a top-gate disposed on a portion of the zero-bandgap graphene layer; " a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate; and " a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate and displaced from the source.
An apparatus comprising: a dual-gate transistor having a negative differential resistance (NDR) region comprising: " a back-gate; " a zero-bandgap graphene layer disposed on the back-gate; " a top-gate disposed on a portion of the zero-bandgap graphene layer; 4 Serial No. 14/268,765 Attorney Docket No. 1186-020/P₁₄₆₀ " a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate; and " a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate and displaced from the source; and a dynamic bias controller adapted to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to cause the dual-gate transistor to operate within the NDR region.
Layer stacks claimed or described, ordered top of device to substrate.
dual-gate graphene transistor with NDR region (G-FET)
graphene-based pattern matching circuit
No layer stack recorded.
apparatus with dual-gate transistor and dynamic bias controller
Materials described outside the worked examples.
zero-bandgap graphene
C
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 50–70 V | — |
Voltage | 1–2 V |
Patent
Atlas literature
Patent
US 9,197,215Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A dual-gate transistor having a negative differential resistance (NDR) region comprising: " a back-gate; " a zero-bandgap graphene layer disposed on the back-gate; " a top-gate disposed on a portion of the zero-bandgap graphene layer; " a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate; and " a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate and displaced from the source, wherein the zero-bandgap graphene layer operates in the NDR region when a source-drain voltage and a top-gate voltage are simultaneously swept across a Dirac point.
The dual-gate transistor of claim 1 wherein the zero-bandgap graphene layer is made up of pristine graphene.
The dual-gate transistor of claim 1 wherein NDR is generated in a drift- diffusion regime at a micrometer scale.
The dual-gate transistor of claim 1 wherein NDR is generated in a ballistic regime at a nanometer scale.
The dual-gate transistor of claim 1 wherein the drain and source are diode- connected.
The dual-gate transistor of claim 1 wherein the zero-bandgap graphene layer comprises single layer graphene.
The dual-gate transistor of claim 1 wherein the zero-bandgap graphene layer comprises bilayer graphene.
Cancelled.
The dual-gate transistor of claim [[2]] 1 wherein a sweeping range for the top-gate voltage and the source-drain voltage is defined by a top-gate capacitance in a position of the Dirac point.
A graphene-based pattern matching circuit comprising: " a plurality of elementary cells coupled in series, each elementary cell comprising: " a first G-FET having a first back-gate that is a first input; " a second G-FET having a second back-gate that is a second input; and " a third G-FET having a current output coupled in series with an adjacent one of the plurality of elementary cells and a third back-gate that is coupled to top-gates of the first G-FET and the second G-FET.
The graphene-based pattern matching circuit of claim 11 wherein current flowing through the third G-FET decreases with a decrease of a Hamming distance between an input data string coupled to the first input and a reference data string coupled to the second input.
The graphene-based pattern matching circuit of claim 11 having an operational frequency range of from around about 100 GHz to around about 500 GHz.
The graphene-based pattern matching circuit of claim 11 having a maximum pattern matching throughput of around about 1022 bits/s/cm2.
The graphene-based pattern matching circuit of claim 11 wherein each of the plurality of elementary cells provides an exclusive OR (XOR) function.
The graphene-based pattern matching circuit of claim 11 wherein each G- FET is a dual-gate transistor having an NDR region comprising: " a back-gate; " a zero-bandgap graphene layer disposed on the back-gate; " a top-gate disposed on a portion of the zero-bandgap graphene layer; " a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate; and " a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate and displaced from the source.
An apparatus comprising: a dual-gate transistor having a negative differential resistance (NDR) region comprising: " a back-gate; " a zero-bandgap graphene layer disposed on the back-gate; " a top-gate disposed on a portion of the zero-bandgap graphene layer; 4 Serial No. 14/268,765 Attorney Docket No. 1186-020/P₁₄₆₀ " a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate; and " a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate and displaced from the source; and a dynamic bias controller adapted to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to cause the dual-gate transistor to operate within the NDR region.
Layer stacks claimed or described, ordered top of device to substrate.
dual-gate graphene transistor with NDR region (G-FET)
graphene-based pattern matching circuit
No layer stack recorded.
apparatus with dual-gate transistor and dynamic bias controller
Materials described outside the worked examples.
zero-bandgap graphene
C
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 50–70 V | — |
Voltage | 1–2 V |
Patent
Atlas literature
Patent
US 9,197,215Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A dual-gate transistor having a negative differential resistance (NDR) region comprising: " a back-gate; " a zero-bandgap graphene layer disposed on the back-gate; " a top-gate disposed on a portion of the zero-bandgap graphene layer; " a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate; and " a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate and displaced from the source, wherein the zero-bandgap graphene layer operates in the NDR region when a source-drain voltage and a top-gate voltage are simultaneously swept across a Dirac point.
The dual-gate transistor of claim 1 wherein the zero-bandgap graphene layer is made up of pristine graphene.
The dual-gate transistor of claim 1 wherein NDR is generated in a drift- diffusion regime at a micrometer scale.
The dual-gate transistor of claim 1 wherein NDR is generated in a ballistic regime at a nanometer scale.
The dual-gate transistor of claim 1 wherein the drain and source are diode- connected.
The dual-gate transistor of claim 1 wherein the zero-bandgap graphene layer comprises single layer graphene.
The dual-gate transistor of claim 1 wherein the zero-bandgap graphene layer comprises bilayer graphene.
Cancelled.
The dual-gate transistor of claim [[2]] 1 wherein a sweeping range for the top-gate voltage and the source-drain voltage is defined by a top-gate capacitance in a position of the Dirac point.
A graphene-based pattern matching circuit comprising: " a plurality of elementary cells coupled in series, each elementary cell comprising: " a first G-FET having a first back-gate that is a first input; " a second G-FET having a second back-gate that is a second input; and " a third G-FET having a current output coupled in series with an adjacent one of the plurality of elementary cells and a third back-gate that is coupled to top-gates of the first G-FET and the second G-FET.
The graphene-based pattern matching circuit of claim 11 wherein current flowing through the third G-FET decreases with a decrease of a Hamming distance between an input data string coupled to the first input and a reference data string coupled to the second input.
The graphene-based pattern matching circuit of claim 11 having an operational frequency range of from around about 100 GHz to around about 500 GHz.
The graphene-based pattern matching circuit of claim 11 having a maximum pattern matching throughput of around about 1022 bits/s/cm2.
The graphene-based pattern matching circuit of claim 11 wherein each of the plurality of elementary cells provides an exclusive OR (XOR) function.
The graphene-based pattern matching circuit of claim 11 wherein each G- FET is a dual-gate transistor having an NDR region comprising: " a back-gate; " a zero-bandgap graphene layer disposed on the back-gate; " a top-gate disposed on a portion of the zero-bandgap graphene layer; " a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate; and " a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate and displaced from the source.
An apparatus comprising: a dual-gate transistor having a negative differential resistance (NDR) region comprising: " a back-gate; " a zero-bandgap graphene layer disposed on the back-gate; " a top-gate disposed on a portion of the zero-bandgap graphene layer; 4 Serial No. 14/268,765 Attorney Docket No. 1186-020/P₁₄₆₀ " a source disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate; and " a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top- gate and displaced from the source; and a dynamic bias controller adapted to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to cause the dual-gate transistor to operate within the NDR region.
Layer stacks claimed or described, ordered top of device to substrate.
dual-gate graphene transistor with NDR region (G-FET)
graphene-based pattern matching circuit
No layer stack recorded.
apparatus with dual-gate transistor and dynamic bias controller
Materials described outside the worked examples.
zero-bandgap graphene
C
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 50–70 V | — |
Voltage | 1–2 V |
| — |
Voltage | 1-0.5 V | — |
Voltage | ≤ 0.5 V | — |
| — |
Voltage | 1-0.5 V | — |
Voltage | ≤ 0.5 V | — |
| — |
Voltage | 1-0.5 V | — |
Voltage | ≤ 0.5 V | — |
| — |
Voltage | 1-0.5 V | — |
Voltage | ≤ 0.5 V | — |