Patent
US 11,694,981 B2DIELECTRIC MOLDED INDIUM BUMP FORMATION AND INP PLANARIZATION
Martin H Ettenberg, Michael Lange
Princeton Infrared Technologies, Inc., Monmouth Junction, NJ (US)·Jul. 4, 2023·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 11,694,981 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a scanning electron microscope image of thick silicon dioxide layer (a dielectric) etched with deep via columns.
FIG. 2 is a diagram of a semiconductor wafer with dielectric vias for deposition of the indium.
FIG. 3b is a diagram of a semiconductor wafer showing well-formed small pitch tall indium bumps following removal of the dielectric.
FIG. 4 is a diagram of a semiconductor wafer that shows a top view of indium columns with trenches etched around each column of indium.
FIG. 5a is a diagram of a semiconductor wafer showing Indium bumps being pressed together after the dielectric is removed.
FIG. 6a is a diagram of a semiconductor wafer showing two-sided indium bumps for hybridization with dielectric barriers to prevent lateral shorting.
FIG. 7 is a diagram of a semiconductor wafer processed into devices with metal interconnects exhibiting bowing.
FIG. 8 is a diagram of a semiconductor wafer on which a dielectric film is deposited and the surface planarized.
FIG. 9 is a diagram of a semiconductor wafer with open holes through dielectric layer to expose semiconductor device contacts.
FIG. 10 is a diagram of a semiconductor wafer on which a second dielectric film is deposited across the wafer surface.
FIG. 11 is a diagram of a semiconductor wafer where the open holes are filled with indium.
FIG. 12 is a diagram of a semiconductor wafer where the dielectric film has been removed, exposing the indium bumps.
FIG. 13B is a diagram that shows trenches in the dielectric to prevent lateral indium shorting during hybridization.
FIG. 14A is a diagram that shows trenches and/or moats around each indium bump or Cu column with the dielectric acting as the walls of the moat between each …
FIG. 20 6b described in more detail below, from coming into contact with neighboring columns when the indium is compressed by the copper posts or indium …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device, the method comprising: depositing a dielectric film having a thickness of greater than 2 micrometers on a semiconductor wafer; opening holes through the dielectric film; depositing indium or an alloy of indium in the holes; melting the indium or alloy of indium deposited in the holes to form indium columns that are uniform in size and shape; repeating the depositing and melting of the indium or alloy of indium until the indium columns reach a desired height; and removing at least a portion of the dielectric film to expose a plurality of substantially uniform indium columns on a surface of the semiconductor wafer having a pitch of less than 15 micrometers.
The method according to claim 1, further comprising planarizing the dielectric film surface prior to opening holes through the dielectric film.
The method according to claim 1, further comprising depositing photo resist on the dielectric film prior to depos-iting the indium or alloy of indium.
The method according to claim 1, wherein the semiconductor wafer is a first semiconductor wafer, the method further comprising hybridizing the first semiconductor wafer to a second semiconductor wafer, wherein the second semiconductor wafer includes a dielectric layer deposited thereon in which a plurality of metal contacts, by pressing the indium columns of the first planarized semiconductor wafer into the metal contacts of the second planarized semicon-ductor layer.
A method of fabricating a semiconductor device, the method comprising: depositing a plurality of metal contacts onto a semicon-ductor wafer; depositing a first dielectric film on the semiconductor wafer; planarizing a surface of the first dielectric film; opening holes through the first dielectric film; depositing a first metal in the holes to form first metal columns such that the top of the first metal columns is flush with the surface of the first dielectric film; depositing a second dielectric film having a thickness greater than 2 micrometers on the first dielectric film; opening holes in the second dielectric film above the first metal columns depositing a second metal in the holes of the second dielectric film; melting the second metal deposited in the holes to form second metal columns that are uniform in size and shape; repeating the depositing and melting of the second metal until the second metal columns reach a desired height; and B₂ removing at least a portion of the second dielectric film to expose a plurality of substantially uniform second metal columns that are in direct electrical contact with the metal contacts on a surface of the semiconductor wafer, wherein the second metal columns have a pitch of less than 15 micrometers.
The method according to claim 10 wherein the first metal is copper or aluminum and the second metal is indium or an alloy of indium.
A hybridized semiconductor device comprising: a first semiconductor wafer comprising: a planarized surface; a plurality of flat, substantially uniform indium col-umns deposited on the planarized surface of the first semiconductor wafer and having a pitch of less than 15 micrometers; and a plurality of trenches surrounding the indium columns bounded by walls of a partially removed dielectric layer in which the indium columns were formed; and a second semiconductor wafer comprising: a planarized surface; a plurality of flat, substantially uniform metal columns deposited on the planarized surface of the second semiconductor wafer and having a pitch that matches that of the indium columns deposited on the first semiconductor wafer; and a plurality of trenches surrounding the metal columns bounded by walls of a partially removed dielectric layer in which the metal columns were formed; wherein the hybridized semiconductor device is con-structed by pressing the second semiconductor wafer into the first semiconductor wafer such that the metal columns are pressed into the indium columns to estab-lish electrical contact between the first and second semiconductor wafers. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor wafer with indium columns in dielectric mold
hybridized semiconductor device (two wafer stack)
Materials described outside the worked examples.
indium or alloy of indium
In
dielectric film
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a scanning electron microscope image of thick silicon dioxide layer (a dielectric) etched with deep via columns.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 8–12 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Patent
Atlas literature
Patent
US 11,694,981 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a scanning electron microscope image of thick silicon dioxide layer (a dielectric) etched with deep via columns.
FIG. 2 is a diagram of a semiconductor wafer with dielectric vias for deposition of the indium.
FIG. 3b is a diagram of a semiconductor wafer showing well-formed small pitch tall indium bumps following removal of the dielectric.
FIG. 4 is a diagram of a semiconductor wafer that shows a top view of indium columns with trenches etched around each column of indium.
FIG. 5a is a diagram of a semiconductor wafer showing Indium bumps being pressed together after the dielectric is removed.
FIG. 6a is a diagram of a semiconductor wafer showing two-sided indium bumps for hybridization with dielectric barriers to prevent lateral shorting.
FIG. 7 is a diagram of a semiconductor wafer processed into devices with metal interconnects exhibiting bowing.
FIG. 8 is a diagram of a semiconductor wafer on which a dielectric film is deposited and the surface planarized.
FIG. 9 is a diagram of a semiconductor wafer with open holes through dielectric layer to expose semiconductor device contacts.
FIG. 10 is a diagram of a semiconductor wafer on which a second dielectric film is deposited across the wafer surface.
FIG. 11 is a diagram of a semiconductor wafer where the open holes are filled with indium.
FIG. 12 is a diagram of a semiconductor wafer where the dielectric film has been removed, exposing the indium bumps.
FIG. 13B is a diagram that shows trenches in the dielectric to prevent lateral indium shorting during hybridization.
FIG. 14A is a diagram that shows trenches and/or moats around each indium bump or Cu column with the dielectric acting as the walls of the moat between each …
FIG. 20 6b described in more detail below, from coming into contact with neighboring columns when the indium is compressed by the copper posts or indium …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device, the method comprising: depositing a dielectric film having a thickness of greater than 2 micrometers on a semiconductor wafer; opening holes through the dielectric film; depositing indium or an alloy of indium in the holes; melting the indium or alloy of indium deposited in the holes to form indium columns that are uniform in size and shape; repeating the depositing and melting of the indium or alloy of indium until the indium columns reach a desired height; and removing at least a portion of the dielectric film to expose a plurality of substantially uniform indium columns on a surface of the semiconductor wafer having a pitch of less than 15 micrometers.
The method according to claim 1, further comprising planarizing the dielectric film surface prior to opening holes through the dielectric film.
The method according to claim 1, further comprising depositing photo resist on the dielectric film prior to depos-iting the indium or alloy of indium.
The method according to claim 1, wherein the semiconductor wafer is a first semiconductor wafer, the method further comprising hybridizing the first semiconductor wafer to a second semiconductor wafer, wherein the second semiconductor wafer includes a dielectric layer deposited thereon in which a plurality of metal contacts, by pressing the indium columns of the first planarized semiconductor wafer into the metal contacts of the second planarized semicon-ductor layer.
A method of fabricating a semiconductor device, the method comprising: depositing a plurality of metal contacts onto a semicon-ductor wafer; depositing a first dielectric film on the semiconductor wafer; planarizing a surface of the first dielectric film; opening holes through the first dielectric film; depositing a first metal in the holes to form first metal columns such that the top of the first metal columns is flush with the surface of the first dielectric film; depositing a second dielectric film having a thickness greater than 2 micrometers on the first dielectric film; opening holes in the second dielectric film above the first metal columns depositing a second metal in the holes of the second dielectric film; melting the second metal deposited in the holes to form second metal columns that are uniform in size and shape; repeating the depositing and melting of the second metal until the second metal columns reach a desired height; and B₂ removing at least a portion of the second dielectric film to expose a plurality of substantially uniform second metal columns that are in direct electrical contact with the metal contacts on a surface of the semiconductor wafer, wherein the second metal columns have a pitch of less than 15 micrometers.
The method according to claim 10 wherein the first metal is copper or aluminum and the second metal is indium or an alloy of indium.
A hybridized semiconductor device comprising: a first semiconductor wafer comprising: a planarized surface; a plurality of flat, substantially uniform indium col-umns deposited on the planarized surface of the first semiconductor wafer and having a pitch of less than 15 micrometers; and a plurality of trenches surrounding the indium columns bounded by walls of a partially removed dielectric layer in which the indium columns were formed; and a second semiconductor wafer comprising: a planarized surface; a plurality of flat, substantially uniform metal columns deposited on the planarized surface of the second semiconductor wafer and having a pitch that matches that of the indium columns deposited on the first semiconductor wafer; and a plurality of trenches surrounding the metal columns bounded by walls of a partially removed dielectric layer in which the metal columns were formed; wherein the hybridized semiconductor device is con-structed by pressing the second semiconductor wafer into the first semiconductor wafer such that the metal columns are pressed into the indium columns to estab-lish electrical contact between the first and second semiconductor wafers. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor wafer with indium columns in dielectric mold
hybridized semiconductor device (two wafer stack)
Materials described outside the worked examples.
indium or alloy of indium
In
dielectric film
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a scanning electron microscope image of thick silicon dioxide layer (a dielectric) etched with deep via columns.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 8–12 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Patent
Atlas literature
Patent
US 11,694,981 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a scanning electron microscope image of thick silicon dioxide layer (a dielectric) etched with deep via columns.
FIG. 2 is a diagram of a semiconductor wafer with dielectric vias for deposition of the indium.
FIG. 3b is a diagram of a semiconductor wafer showing well-formed small pitch tall indium bumps following removal of the dielectric.
FIG. 4 is a diagram of a semiconductor wafer that shows a top view of indium columns with trenches etched around each column of indium.
FIG. 5a is a diagram of a semiconductor wafer showing Indium bumps being pressed together after the dielectric is removed.
FIG. 6a is a diagram of a semiconductor wafer showing two-sided indium bumps for hybridization with dielectric barriers to prevent lateral shorting.
FIG. 7 is a diagram of a semiconductor wafer processed into devices with metal interconnects exhibiting bowing.
FIG. 8 is a diagram of a semiconductor wafer on which a dielectric film is deposited and the surface planarized.
FIG. 9 is a diagram of a semiconductor wafer with open holes through dielectric layer to expose semiconductor device contacts.
FIG. 10 is a diagram of a semiconductor wafer on which a second dielectric film is deposited across the wafer surface.
FIG. 11 is a diagram of a semiconductor wafer where the open holes are filled with indium.
FIG. 12 is a diagram of a semiconductor wafer where the dielectric film has been removed, exposing the indium bumps.
FIG. 13B is a diagram that shows trenches in the dielectric to prevent lateral indium shorting during hybridization.
FIG. 14A is a diagram that shows trenches and/or moats around each indium bump or Cu column with the dielectric acting as the walls of the moat between each …
FIG. 20 6b described in more detail below, from coming into contact with neighboring columns when the indium is compressed by the copper posts or indium …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device, the method comprising: depositing a dielectric film having a thickness of greater than 2 micrometers on a semiconductor wafer; opening holes through the dielectric film; depositing indium or an alloy of indium in the holes; melting the indium or alloy of indium deposited in the holes to form indium columns that are uniform in size and shape; repeating the depositing and melting of the indium or alloy of indium until the indium columns reach a desired height; and removing at least a portion of the dielectric film to expose a plurality of substantially uniform indium columns on a surface of the semiconductor wafer having a pitch of less than 15 micrometers.
The method according to claim 1, further comprising planarizing the dielectric film surface prior to opening holes through the dielectric film.
The method according to claim 1, further comprising depositing photo resist on the dielectric film prior to depos-iting the indium or alloy of indium.
The method according to claim 1, wherein the semiconductor wafer is a first semiconductor wafer, the method further comprising hybridizing the first semiconductor wafer to a second semiconductor wafer, wherein the second semiconductor wafer includes a dielectric layer deposited thereon in which a plurality of metal contacts, by pressing the indium columns of the first planarized semiconductor wafer into the metal contacts of the second planarized semicon-ductor layer.
A method of fabricating a semiconductor device, the method comprising: depositing a plurality of metal contacts onto a semicon-ductor wafer; depositing a first dielectric film on the semiconductor wafer; planarizing a surface of the first dielectric film; opening holes through the first dielectric film; depositing a first metal in the holes to form first metal columns such that the top of the first metal columns is flush with the surface of the first dielectric film; depositing a second dielectric film having a thickness greater than 2 micrometers on the first dielectric film; opening holes in the second dielectric film above the first metal columns depositing a second metal in the holes of the second dielectric film; melting the second metal deposited in the holes to form second metal columns that are uniform in size and shape; repeating the depositing and melting of the second metal until the second metal columns reach a desired height; and B₂ removing at least a portion of the second dielectric film to expose a plurality of substantially uniform second metal columns that are in direct electrical contact with the metal contacts on a surface of the semiconductor wafer, wherein the second metal columns have a pitch of less than 15 micrometers.
The method according to claim 10 wherein the first metal is copper or aluminum and the second metal is indium or an alloy of indium.
A hybridized semiconductor device comprising: a first semiconductor wafer comprising: a planarized surface; a plurality of flat, substantially uniform indium col-umns deposited on the planarized surface of the first semiconductor wafer and having a pitch of less than 15 micrometers; and a plurality of trenches surrounding the indium columns bounded by walls of a partially removed dielectric layer in which the indium columns were formed; and a second semiconductor wafer comprising: a planarized surface; a plurality of flat, substantially uniform metal columns deposited on the planarized surface of the second semiconductor wafer and having a pitch that matches that of the indium columns deposited on the first semiconductor wafer; and a plurality of trenches surrounding the metal columns bounded by walls of a partially removed dielectric layer in which the metal columns were formed; wherein the hybridized semiconductor device is con-structed by pressing the second semiconductor wafer into the first semiconductor wafer such that the metal columns are pressed into the indium columns to estab-lish electrical contact between the first and second semiconductor wafers. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor wafer with indium columns in dielectric mold
hybridized semiconductor device (two wafer stack)
Materials described outside the worked examples.
indium or alloy of indium
In
dielectric film
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a scanning electron microscope image of thick silicon dioxide layer (a dielectric) etched with deep via columns.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 8–12 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Patent
Atlas literature
Patent
US 11,694,981 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a scanning electron microscope image of thick silicon dioxide layer (a dielectric) etched with deep via columns.
FIG. 2 is a diagram of a semiconductor wafer with dielectric vias for deposition of the indium.
FIG. 3b is a diagram of a semiconductor wafer showing well-formed small pitch tall indium bumps following removal of the dielectric.
FIG. 4 is a diagram of a semiconductor wafer that shows a top view of indium columns with trenches etched around each column of indium.
FIG. 5a is a diagram of a semiconductor wafer showing Indium bumps being pressed together after the dielectric is removed.
FIG. 6a is a diagram of a semiconductor wafer showing two-sided indium bumps for hybridization with dielectric barriers to prevent lateral shorting.
FIG. 7 is a diagram of a semiconductor wafer processed into devices with metal interconnects exhibiting bowing.
FIG. 8 is a diagram of a semiconductor wafer on which a dielectric film is deposited and the surface planarized.
FIG. 9 is a diagram of a semiconductor wafer with open holes through dielectric layer to expose semiconductor device contacts.
FIG. 10 is a diagram of a semiconductor wafer on which a second dielectric film is deposited across the wafer surface.
FIG. 11 is a diagram of a semiconductor wafer where the open holes are filled with indium.
FIG. 12 is a diagram of a semiconductor wafer where the dielectric film has been removed, exposing the indium bumps.
FIG. 13B is a diagram that shows trenches in the dielectric to prevent lateral indium shorting during hybridization.
FIG. 14A is a diagram that shows trenches and/or moats around each indium bump or Cu column with the dielectric acting as the walls of the moat between each …
FIG. 20 6b described in more detail below, from coming into contact with neighboring columns when the indium is compressed by the copper posts or indium …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device, the method comprising: depositing a dielectric film having a thickness of greater than 2 micrometers on a semiconductor wafer; opening holes through the dielectric film; depositing indium or an alloy of indium in the holes; melting the indium or alloy of indium deposited in the holes to form indium columns that are uniform in size and shape; repeating the depositing and melting of the indium or alloy of indium until the indium columns reach a desired height; and removing at least a portion of the dielectric film to expose a plurality of substantially uniform indium columns on a surface of the semiconductor wafer having a pitch of less than 15 micrometers.
The method according to claim 1, further comprising planarizing the dielectric film surface prior to opening holes through the dielectric film.
The method according to claim 1, further comprising depositing photo resist on the dielectric film prior to depos-iting the indium or alloy of indium.
The method according to claim 1, wherein the semiconductor wafer is a first semiconductor wafer, the method further comprising hybridizing the first semiconductor wafer to a second semiconductor wafer, wherein the second semiconductor wafer includes a dielectric layer deposited thereon in which a plurality of metal contacts, by pressing the indium columns of the first planarized semiconductor wafer into the metal contacts of the second planarized semicon-ductor layer.
A method of fabricating a semiconductor device, the method comprising: depositing a plurality of metal contacts onto a semicon-ductor wafer; depositing a first dielectric film on the semiconductor wafer; planarizing a surface of the first dielectric film; opening holes through the first dielectric film; depositing a first metal in the holes to form first metal columns such that the top of the first metal columns is flush with the surface of the first dielectric film; depositing a second dielectric film having a thickness greater than 2 micrometers on the first dielectric film; opening holes in the second dielectric film above the first metal columns depositing a second metal in the holes of the second dielectric film; melting the second metal deposited in the holes to form second metal columns that are uniform in size and shape; repeating the depositing and melting of the second metal until the second metal columns reach a desired height; and B₂ removing at least a portion of the second dielectric film to expose a plurality of substantially uniform second metal columns that are in direct electrical contact with the metal contacts on a surface of the semiconductor wafer, wherein the second metal columns have a pitch of less than 15 micrometers.
The method according to claim 10 wherein the first metal is copper or aluminum and the second metal is indium or an alloy of indium.
A hybridized semiconductor device comprising: a first semiconductor wafer comprising: a planarized surface; a plurality of flat, substantially uniform indium col-umns deposited on the planarized surface of the first semiconductor wafer and having a pitch of less than 15 micrometers; and a plurality of trenches surrounding the indium columns bounded by walls of a partially removed dielectric layer in which the indium columns were formed; and a second semiconductor wafer comprising: a planarized surface; a plurality of flat, substantially uniform metal columns deposited on the planarized surface of the second semiconductor wafer and having a pitch that matches that of the indium columns deposited on the first semiconductor wafer; and a plurality of trenches surrounding the metal columns bounded by walls of a partially removed dielectric layer in which the metal columns were formed; wherein the hybridized semiconductor device is con-structed by pressing the second semiconductor wafer into the first semiconductor wafer such that the metal columns are pressed into the indium columns to estab-lish electrical contact between the first and second semiconductor wafers. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor wafer with indium columns in dielectric mold
hybridized semiconductor device (two wafer stack)
Materials described outside the worked examples.
indium or alloy of indium
In
dielectric film
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a scanning electron microscope image of thick silicon dioxide layer (a dielectric) etched with deep via columns.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 8–12 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
semiconductor wafer with two-level metal column stack
dielectric film (silicon dioxide or silicon nitride)
metal columns (generic)
copper
Cu
aluminum
Al
photo resist
| 10–15 µm |
| — |
Thickness | 6–10 µm | — |
Temperature | 300–400 °C | — |
Thickness | 3–10 µm | — |
Thickness | ≤ 10 µm | — |
Thickness | ≤ 5 µm | — |
Thickness | ≤ 4 µm | — |
Thickness | ≤ 2 µm | — |
Thickness | ≤ 7 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≥ 10 µm | — |
Thickness | ≥ 8 µm | — |
Thickness | ≤ 15 µm | — |
Thickness | ≥ 2 µm | — |
Thickness | 2–30 um | — |
semiconductor wafer with two-level metal column stack
dielectric film (silicon dioxide or silicon nitride)
metal columns (generic)
copper
Cu
aluminum
Al
photo resist
| 10–15 µm |
| — |
Thickness | 6–10 µm | — |
Temperature | 300–400 °C | — |
Thickness | 3–10 µm | — |
Thickness | ≤ 10 µm | — |
Thickness | ≤ 5 µm | — |
Thickness | ≤ 4 µm | — |
Thickness | ≤ 2 µm | — |
Thickness | ≤ 7 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≥ 10 µm | — |
Thickness | ≥ 8 µm | — |
Thickness | ≤ 15 µm | — |
Thickness | ≥ 2 µm | — |
Thickness | 2–30 um | — |
semiconductor wafer with two-level metal column stack
dielectric film (silicon dioxide or silicon nitride)
metal columns (generic)
copper
Cu
aluminum
Al
photo resist
| 10–15 µm |
| — |
Thickness | 6–10 µm | — |
Temperature | 300–400 °C | — |
Thickness | 3–10 µm | — |
Thickness | ≤ 10 µm | — |
Thickness | ≤ 5 µm | — |
Thickness | ≤ 4 µm | — |
Thickness | ≤ 2 µm | — |
Thickness | ≤ 7 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≥ 10 µm | — |
Thickness | ≥ 8 µm | — |
Thickness | ≤ 15 µm | — |
Thickness | ≥ 2 µm | — |
Thickness | 2–30 um | — |
semiconductor wafer with two-level metal column stack
dielectric film (silicon dioxide or silicon nitride)
metal columns (generic)
copper
Cu
aluminum
Al
photo resist
| 10–15 µm |
| — |
Thickness | 6–10 µm | — |
Temperature | 300–400 °C | — |
Thickness | 3–10 µm | — |
Thickness | ≤ 10 µm | — |
Thickness | ≤ 5 µm | — |
Thickness | ≤ 4 µm | — |
Thickness | ≤ 2 µm | — |
Thickness | ≤ 7 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≥ 10 µm | — |
Thickness | ≥ 8 µm | — |
Thickness | ≤ 15 µm | — |
Thickness | ≥ 2 µm | — |
Thickness | 2–30 um | — |